aiot/waterDataPreprocessing/databaseOperation/dataSynchronizationMemory.h

/*
 * bfin_can.h - interface to Blackfin CANs
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __ASM_BFIN_CAN_H__
#define __ASM_BFIN_CAN_H__

/*
 * transmit and receive channels
 */
#define TRANSMIT_CHL            24
#define RECEIVE_STD_CHL         0
#define RECEIVE_EXT_CHL         4
#define RECEIVE_RTR_CHL         8
#define RECEIVE_EXT_RTR_CHL     12
#define MAX_CHL_NUMBER          32

/*
 * All Blackfin system MMRs are padded to 32bits even if the register
 * itself is only 16bits.  So use a helper macro to streamline this.
 */
#define __BFP(m) u16 m; u16 __pad_##m

/*
 * bfin can registers layout
 */
struct bfin_can_mask_regs {
	__BFP(aml);
	__BFP(amh);
};

struct bfin_can_channel_regs {
	/* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
	u16 data[8];
	__BFP(dlc);
	__BFP(tsv);
	__BFP(id0);
	__BFP(id1);
};

struct bfin_can_regs {
	/*
	 * global control and status registers
	 */
	__BFP(mc1);           /* offset 0x00 */
	__BFP(md1);           /* offset 0x04 */
	__BFP(trs1);          /* offset 0x08 */
	__BFP(trr1);          /* offset 0x0c */
	__BFP(ta1);           /* offset 0x10 */
	__BFP(aa1);           /* offset 0x14 */
	__BFP(rmp1);          /* offset 0x18 */
	__BFP(rml1);          /* offset 0x1c */
	__BFP(mbtif1);        /* offset 0x20 */
	__BFP(mbrif1);        /* offset 0x24 */
	__BFP(mbim1);         /* offset 0x28 */
	__BFP(rfh1);          /* offset 0x2c */
	__BFP(opss1);         /* offset 0x30 */
	u32 __pad1[3];
	__BFP(mc2);           /* offset 0x40 */
	__BFP(md2);           /* offset 0x44 */
	__BFP(trs2);          /* offset 0x48 */
	__BFP(trr2);          /* offset 0x4c */
	__BFP(ta2);           /* offset 0x50 */
	__BFP(aa2);           /* offset 0x54 */
	__BFP(rmp2);          /* offset 0x58 */
	__BFP(rml2);          /* offset 0x5c */
	__BFP(mbtif2);        /* offset 0x60 */
	__BFP(mbrif2);        /* offset 0x64 */
	__BFP(mbim2);         /* offset 0x68 */
	__BFP(rfh2);          /* offset 0x6c */
	__BFP(opss2);         /* offset 0x70 */
	u32 __pad2[3];
	__BFP(clock);         /* offset 0x80 */
	__BFP(timing);        /* offset 0x84 */
	__BFP(debug);         /* offset 0x88 */
	__BFP(status);        /* offset 0x8c */
	__BFP(cec);           /* offset 0x90 */
	__BFP(gis);           /* offset 0x94 */
	__BFP(gim);           /* offset 0x98 */
	__BFP(gif);           /* offset 0x9c */
	__BFP(control);       /* offset 0xa0 */
	__BFP(intr);          /* offset 0xa4 */
	__BFP(version);       /* offset 0xa8 */
	__BFP(mbtd);          /* offset 0xac */
	__BFP(ewr);           /* offset 0xb0 */
	__BFP(esr);           /* offset 0xb4 */
	u32 __pad3[2];
	__BFP(ucreg);         /* offset 0xc0 */
	__BFP(uccnt);         /* offset 0xc4 */
	__BFP(ucrc);          /* offset 0xc8 */
	__BFP(uccnf);         /* offset 0xcc */
	u32 __pad4[1];
	__BFP(version2);      /* offset 0xd4 */
	u32 __pad5[10];

	/*
	 * channel(mailbox) mask and message registers
	 */
	struct bfin_can_mask_regs msk[MAX_CHL_NUMBER];    /* offset 0x100 */
	struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
};

#undef __BFP

/* CAN_CONTROL Masks */
#define SRS			0x0001	/* Software Reset */
#define DNM			0x0002	/* Device Net Mode */
#define ABO			0x0004	/* Auto-Bus On Enable */
#define TXPRIO		0x0008	/* TX Priority (Priority/Mailbox*) */
#define WBA			0x0010	/* Wake-Up On CAN Bus Activity Enable */
#define SMR			0x0020	/* Sleep Mode Request */
#define CSR			0x0040	/* CAN Suspend Mode Request */
#define CCR			0x0080	/* CAN Configuration Mode Request */

/* CAN_STATUS Masks */
#define WT			0x0001	/* TX Warning Flag */
#define WR			0x0002	/* RX Warning Flag */
#define EP			0x0004	/* Error Passive Mode */
#define EBO			0x0008	/* Error Bus Off Mode */
#define SMA			0x0020	/* Sleep Mode Acknowledge */
#define CSA			0x0040	/* Suspend Mode Acknowledge */
#define CCA			0x0080	/* Configuration Mode Acknowledge */
#define MBPTR		0x1F00	/* Mailbox Pointer */
#define TRM			0x4000	/* Transmit Mode */
#define REC			0x8000	/* Receive Mode */

/* CAN_CLOCK Masks */
#define BRP			0x03FF	/* Bit-Rate Pre-Scaler */

/* CAN_TIMING Masks */
#define TSEG1		0x000F	/* Time Segment 1 */
#define TSEG2		0x0070	/* Time Segment 2 */
#define SAM			0x0080	/* Sampling */
#define SJW			0x0300	/* Synchronization Jump Width */

/* CAN_DEBUG Masks */
#define DEC			0x0001	/* Disable CAN Error Counters */
#define DRI			0x0002	/* Disable CAN RX Input */
#define DTO			0x0004	/* Disable CAN TX Output */
#define DIL			0x0008	/* Disable CAN Internal Loop */
#define MAA			0x0010	/* Mode Auto-Acknowledge Enable */
#define MRB			0x0020	/* Mode Read Back Enable */
#define CDE			0x8000	/* CAN Debug Enable */

/* CAN_CEC Masks */
#define RXECNT		0x00FF	/* Receive Error Counter */
#define TXECNT		0xFF00	/* Transmit Error Counter */

/* CAN_INTR Masks */
#define MBRIRQ	0x0001	/* Mailbox Receive Interrupt */
#define MBTIRQ	0x0002	/* Mailbox Transmit Interrupt */
#define GIRQ		0x0004	/* Global Interrupt */
#define SMACK		0x0008	/* Sleep Mode Acknowledge */
#define CANTX		0x0040	/* CAN TX Bus Value */
#define CANRX		0x0080	/* CAN RX Bus Value */

/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
#define DFC			0xFFFF	/* Data Filtering Code (If Enabled) (ID0) */
#define EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (ID0) */
#define EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (ID1) */
#define BASEID		0x1FFC	/* Base Identifier */
#define IDE			0x2000	/* Identifier Extension */
#define RTR			0x4000	/* Remote Frame Transmission Request */
#define AME			0x8000	/* Acceptance Mask Enable */