aiot/efElectricAgingTrendMining/dataSharedMemory/memoryDefinitionAgingAnalysisData.h

/*
 * OMAP3430 Power/Reset Management register bits
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H


#include "prm3xxx.h"

/* Shared register bits */

/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
#define OMAP3430_ON_SHIFT				24
#define OMAP3430_ON_MASK				(0xff << 24)
#define OMAP3430_ONLP_SHIFT				16
#define OMAP3430_ONLP_MASK				(0xff << 16)
#define OMAP3430_RET_SHIFT				8
#define OMAP3430_RET_MASK				(0xff << 8)
#define OMAP3430_OFF_SHIFT				0
#define OMAP3430_OFF_MASK				(0xff << 0)

/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
#define OMAP3430_ERROROFFSET_SHIFT			24
#define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
#define OMAP3430_ERRORGAIN_SHIFT			16
#define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
#define OMAP3430_INITVOLTAGE_SHIFT			8
#define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
#define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
#define OMAP3430_INITVDD_MASK				(1 << 2)
#define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
#define OMAP3430_VPENABLE_MASK				(1 << 0)

/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
#define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
#define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
#define OMAP3430_VSTEPMIN_SHIFT				0
#define OMAP3430_VSTEPMIN_MASK				(0xff << 0)

/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
#define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
#define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
#define OMAP3430_VSTEPMAX_SHIFT				0
#define OMAP3430_VSTEPMAX_MASK				(0xff << 0)

/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
#define OMAP3430_VDDMAX_SHIFT				24
#define OMAP3430_VDDMAX_MASK				(0xff << 24)
#define OMAP3430_VDDMIN_SHIFT				16
#define OMAP3430_VDDMIN_MASK				(0xff << 16)
#define OMAP3430_TIMEOUT_SHIFT				0
#define OMAP3430_TIMEOUT_MASK				(0xffff << 0)

/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
#define OMAP3430_VPVOLTAGE_SHIFT			0
#define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)

/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
#define OMAP3430_VPINIDLE_MASK				(1 << 0)

/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
#define OMAP3430_EN_PER_SHIFT				7
#define OMAP3430_EN_PER_MASK				(1 << 7)

/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
#define OMAP3430_MEMORYCHANGE_MASK			(1 << 3)

/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
#define OMAP3430_LOGICSTATEST_MASK			(1 << 2)

/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
#define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)

/*
 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
 */
#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT		0
#define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)

/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
#define OMAP3430_WKUP_ST_MASK				(1 << 0)

/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
#define OMAP3430_WKUP_EN_MASK				(1 << 0)

/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
#define OMAP3430_GRPSEL_MMC2_MASK			(1 << 25)
#define OMAP3430_GRPSEL_MMC1_MASK			(1 << 24)
#define OMAP3430_GRPSEL_MCSPI4_MASK			(1 << 21)
#define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
#define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
#define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
#define OMAP3430_GRPSEL_I2C3_SHIFT			17
#define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
#define OMAP3430_GRPSEL_I2C2_SHIFT			16
#define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
#define OMAP3430_GRPSEL_I2C1_SHIFT			15
#define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
#define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
#define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
#define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12)
#define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11)
#define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
#define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
#define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4)
#define OMAP3430_GRPSEL_D2D_MASK			(1 << 3)

/*
 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
 * PM_PWSTCTRL_PER shared bits
 */
#define OMAP3430_MEMONSTATE_SHIFT			16
#define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
#define OMAP3430_MEMRETSTATE_MASK			(1 << 8)

/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
#define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
#define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
#define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
#define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
#define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
#define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
#define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
#define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10)
#define OMAP3430_GRPSEL_GPT8_MASK			(1 << 9)
#define OMAP3430_GRPSEL_GPT7_MASK			(1 << 8)
#define OMAP3430_GRPSEL_GPT6_MASK			(1 << 7)
#define OMAP3430_GRPSEL_GPT5_MASK			(1 << 6)
#define OMAP3430_GRPSEL_GPT4_MASK			(1 << 5)
#define OMAP3430_GRPSEL_GPT3_MASK			(1 << 4)
#define OMAP3430_GRPSEL_GPT2_MASK			(1 << 3)
#define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
#define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
#define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)

/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
#define OMAP3430_GRPSEL_IO_MASK				(1 << 8)
#define OMAP3430_GRPSEL_SR2_MASK			(1 << 7)
#define OMAP3430_GRPSEL_SR1_MASK			(1 << 6)
#define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
#define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
#define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)

/* Bits specific to each register */

/* RM_RSTCTRL_IVA2 */
#define OMAP3430_RST3_IVA2_MASK				(1 << 2)
#define OMAP3430_RST2_IVA2_MASK				(1 << 1)
#define OMAP3430_RST1_IVA2_MASK				(1 << 0)

/* RM_RSTST_IVA2 specific bits */
#define OMAP3430_EMULATION_VSEQ_RST_MASK		(1 << 13)
#define OMAP3430_EMULATION_VHWA_RST_MASK		(1 << 12)
#define OMAP3430_EMULATION_IVA2_RST_MASK		(1 << 11)
#define OMAP3430_IVA2_SW_RST3_MASK			(1 << 10)
#define OMAP3430_IVA2_SW_RST2_MASK			(1 << 9)
#define OMAP3430_IVA2_SW_RST1_MASK			(1 << 8)

/* PM_WKDEP_IVA2 specific bits */

/* PM_PWSTCTRL_IVA2 specific bits */
#define OMAP3430_L2FLATMEMONSTATE_SHIFT			22
#define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT		20
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
#define OMAP3430_L1FLATMEMONSTATE_SHIFT			18
#define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT		16
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
#define OMAP3430_L2FLATMEMRETSTATE_MASK			(1 << 11)
#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK		(1 << 10)
#define OMAP3430_L1FLATMEMRETSTATE_MASK			(1 << 9)
#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK		(1 << 8)

/* PM_PWSTST_IVA2 specific bits */
#define OMAP3430_L2FLATMEMSTATEST_SHIFT			10
#define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT		8
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
#define OMAP3430_L1FLATMEMSTATEST_SHIFT			6
#define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT		4
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)

/* PM_PREPWSTST_IVA2 specific bits */
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT		10
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT	8
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT		6
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK			(0x3 << 6)
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT	4
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK		(0x3 << 4)

/* PRM_IRQSTATUS_IVA2 specific bits */
#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK	(1 << 2)
#define OMAP3430_FORCEWKUP_ST_MASK			(1 << 1)

/* PRM_IRQENABLE_IVA2 specific bits */
#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK	(1 << 2)
#define OMAP3430_FORCEWKUP_EN_MASK				(1 << 1)

/* PRM_REVISION specific bits */

/* PRM_SYSCONFIG specific bits */

/* PRM_IRQSTATUS_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK		(1 << 25)
#define OMAP3430_VC_TIMEOUTERR_ST_MASK			(1 << 24)
#define OMAP3430_VC_RAERR_ST_MASK			(1 << 23)
#define OMAP3430_VC_SAERR_ST_MASK			(1 << 22)
#define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
#define OMAP3430_VP2_EQVALUE_ST_MASK			(1 << 20)
#define OMAP3430_VP2_NOSMPSACK_ST_MASK			(1 << 19)
#define OMAP3430_VP2_MAXVDD_ST_MASK			(1 << 18)
#define OMAP3430_VP2_MINVDD_ST_MASK			(1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK		(1 << 16)
#define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
#define OMAP3430_VP1_EQVALUE_ST_MASK			(1 << 14)
#define OMAP3430_VP1_NOSMPSACK_ST_MASK			(1 << 13)
#define OMAP3430_VP1_MAXVDD_ST_MASK			(1 << 12)
#define OMAP3430_VP1_MINVDD_ST_MASK			(1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK		(1 << 10)
#define OMAP3430_IO_ST_MASK				(1 << 9)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK	(1 << 8)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
#define OMAP3430_MPU_DPLL_ST_MASK			(1 << 7)
#define OMAP3430_MPU_DPLL_ST_SHIFT			7
#define OMAP3430_PERIPH_DPLL_ST_MASK			(1 << 6)
#define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
#define OMAP3430_CORE_DPLL_ST_MASK			(1 << 5)
#define OMAP3430_CORE_DPLL_ST_SHIFT			5
#define OMAP3430_TRANSITION_ST_MASK			(1 << 4)
#define OMAP3430_EVGENOFF_ST_MASK			(1 << 3)
#define OMAP3430_EVGENON_ST_MASK			(1 << 2)
#define OMAP3430_FS_USB_WKUP_ST_MASK			(1 << 1)

/* PRM_IRQENABLE_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK		(1 << 25)
#define OMAP3430_VC_TIMEOUTERR_EN_MASK				(1 << 24)
#define OMAP3430_VC_RAERR_EN_MASK				(1 << 23)
#define OMAP3430_VC_SAERR_EN_MASK				(1 << 22)
#define OMAP3430_VP2_TRANXDONE_EN_MASK				(1 << 21)
#define OMAP3430_VP2_EQVALUE_EN_MASK				(1 << 20)
#define OMAP3430_VP2_NOSMPSACK_EN_MASK				(1 << 19)
#define OMAP3430_VP2_MAXVDD_EN_MASK				(1 << 18)
#define OMAP3430_VP2_MINVDD_EN_MASK				(1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK			(1 << 16)
#define OMAP3430_VP1_TRANXDONE_EN_MASK				(1 << 15)
#define OMAP3430_VP1_EQVALUE_EN_MASK				(1 << 14)
#define OMAP3430_VP1_NOSMPSACK_EN_MASK				(1 << 13)
#define OMAP3430_VP1_MAXVDD_EN_MASK				(1 << 12)
#define OMAP3430_VP1_MINVDD_EN_MASK				(1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK			(1 << 10)
#define OMAP3430_IO_EN_MASK					(1 << 9)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK	(1 << 8)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
#define OMAP3430_MPU_DPLL_RECAL_EN_MASK				(1 << 7)
#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK			(1 << 6)
#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
#define OMAP3430_CORE_DPLL_RECAL_EN_MASK			(1 << 5)
#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
#define OMAP3430_TRANSITION_EN_MASK				(1 << 4)
#define OMAP3430_EVGENOFF_EN_MASK				(1 << 3)
#define OMAP3430_EVGENON_EN_MASK				(1 << 2)
#define OMAP3430_FS_USB_WKUP_EN_MASK				(1 << 1)

/* RM_RSTST_MPU specific bits */
#define OMAP3430_EMULATION_MPU_RST_MASK			(1 << 11)

/* PM_WKDEP_MPU specific bits */
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK		(1 << 5)
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK		(1 << 2)

/* PM_EVGENCTRL_MPU */
#define OMAP3430_OFFLOADMODE_SHIFT			3