aiot/waterDataDiscreteRateMining/dataSharedMemory/varianceMemoryDefinition.h

/***********************************
 * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
 ***********************************
 *
 ***************************************
 * Definitions of the QUICC registers
 ***************************************
 */

#ifndef __REGISTERS_H
#define __REGISTERS_H

#define CLEAR_BIT(x, bit)  x =bit 

/*****************************************************************
        Command Register
*****************************************************************/

/* bit fields within command register */
#define SOFTWARE_RESET  0x8000
#define CMD_OPCODE      0x0f00
#define CMD_CHANNEL     0x00f0
#define CMD_FLAG        0x0001

/* general command opcodes */
#define INIT_RXTX_PARAMS        0x0000
#define INIT_RX_PARAMS          0x0100
#define INIT_TX_PARAMS          0x0200
#define ENTER_HUNT_MODE         0x0300
#define STOP_TX                 0x0400
#define GR_STOP_TX              0x0500
#define RESTART_TX              0x0600
#define CLOSE_RX_BD             0x0700
#define SET_ENET_GROUP          0x0800
#define RESET_ENET_GROUP        0x0900

/* quicc32 CP commands */
#define STOP_TX_32		0x0e00	/*add chan# bits 2-6 */
#define ENTER_HUNT_MODE_32	0x1e00

/* quicc32 mask/event SCC register */
#define GOV	0x01
#define GUN	0x02
#define GINT	0x04
#define IQOV	0x08


/* Timer commands */
#define SET_TIMER               0x0800

/* Multi channel Interrupt structure */
#define INTR_VALID	0x8000	/* Valid interrupt entry */
#define INTR_WRAP	0x4000	/* Wrap bit in the interrupt entry table */
#define INTR_CH_NU	0x07c0	/* Channel Num in interrupt table */
#define INTR_MASK_BITS	0x383f

/*
 * General SCC mode register (GSMR)
 */

#define MODE_HDLC               0x0
#define MODE_APPLE_TALK         0x2
#define MODE_SS7                0x3
#define MODE_UART               0x4
#define MODE_PROFIBUS           0x5
#define MODE_ASYNC_HDLC         0x6
#define MODE_V14                0x7
#define MODE_BISYNC             0x8
#define MODE_DDCMP              0x9
#define MODE_MULTI_CHANNEL      0xa
#define MODE_ETHERNET           0xc

#define DIAG_NORMAL             0x0
#define DIAG_LOCAL_LPB          0x1
#define DIAG_AUTO_ECHO          0x2
#define DIAG_LBP_ECHO           0x3

/* For RENC and TENC fields in GSMR */
#define ENC_NRZ                 0x0
#define ENC_NRZI                0x1
#define ENC_FM0                 0x2
#define ENC_MANCH               0x4
#define ENC_DIFF_MANC           0x6

/* For TDCR and RDCR fields in GSMR */
#define CLOCK_RATE_1            0x0
#define CLOCK_RATE_8            0x1
#define CLOCK_RATE_16           0x2
#define CLOCK_RATE_32           0x3

#define TPP_00                  0x0
#define TPP_10                  0x1
#define TPP_01                  0x2
#define TPP_11                  0x3

#define TPL_NO                  0x0
#define TPL_8                   0x1
#define TPL_16                  0x2
#define TPL_32                  0x3
#define TPL_48                  0x4
#define TPL_64                  0x5
#define TPL_128                 0x6

#define TSNC_INFINITE           0x0
#define TSNC_14_65              0x1
#define TSNC_4_15               0x2
#define TSNC_3_1                0x3

#define EDGE_BOTH               0x0
#define EDGE_POS                0x1
#define EDGE_NEG                0x2
#define EDGE_NO                 0x3

#define SYNL_NO                 0x0
#define SYNL_4                  0x1
#define SYNL_8                  0x2
#define SYNL_16                 0x3

#define TCRC_CCITT16            0x0
#define TCRC_CRC16              0x1
#define TCRC_CCITT32            0x2


/*****************************************************************
        TODR (Transmit on demand) Register
*****************************************************************/
#define TODR_TOD        0x8000  /* Transmit on demand */


/*****************************************************************
        CICR register settings
*****************************************************************/

/* note that relative irq priorities of the SCCs can be reordered
 * if desired - see p. 7-377 of the MC68360UM */
#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */