| 1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556 |
- /*
- * Analog Devices SPI3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
- #ifndef _SPI_CHANNEL_H_
- #define _SPI_CHANNEL_H_
- #include <linux/types.h>
- /* SPI_CONTROL */
- #define SPI_CTL_EN 0x00000001 /* Enable */
- #define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
- #define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
- #define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
- #define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
- #define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
- #define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
- #define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
- #define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
- #define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
- #define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
- #define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
- #define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
- #define SPI_CTL_LSBF 0x00001000 /* LSB First */
- #define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
- #define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
- #define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
- #define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
- #define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
- #define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
- #define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
- #define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
- #define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
- #define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
- #define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
- #define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
- #define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
- /* SPI_RX_CONTROL */
- #define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
- #define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
- #define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
|
