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efHeterogeneousSynchronization
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dataSharedMemory
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memoryOperation.h

memoryOperation.h 4.3 KB
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  1. #ifndef __ALPHA_T2__H__
    2. 

  2. #define __ALPHA_T2__H__
    3. 

  3. 

  4. /* Fit everything into one 128MB HAE window. */
    5. 

  5. #define T2_ONE_HAE_WINDOW 1
    6. 

  6. 

  7. #include <linux/types.h>
    8. 

  8. #include <linux/spinlock.h>
    9. 

  9. #include <asm/compiler.h>
    10. 

  10. 

  11. /*
    12. 

  12.  * T2 is the internal name for the core logic chipset which provides
    13. 

  13.  * memory controller and PCI access for the SABLE-based systems.
    14. 

  14.  *
    15. 

  15.  * This file is based on:
    16. 

  16.  *
    17. 

  17.  * SABLE I/O Specification
    18. 

  18.  * Revision/Update Information: 1.3
    19. 

  19.  *
    20. 

  20.  * jestabro@amt.tay1.dec.com Initial Version.
    21. 

  21.  *
    22. 

  22.  */
    23. 

  23. 

  24. #define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 27 bits */
    25. 

  25. 

  26. /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
    27. 

  27. /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
    28. 

  28. #define _GAMMA_BIAS		0x8000000000UL
    29. 

  29. 

  30. #if defined(CONFIG_ALPHA_GENERIC)
    31. 

  31. #define GAMMA_BIAS		alpha_mv.sys.t2.gamma_bias
    32. 

  32. #elif defined(CONFIG_ALPHA_GAMMA)
    33. 

  33. #define GAMMA_BIAS		_GAMMA_BIAS
    34. 

  34. #else
    35. 

  35. #define GAMMA_BIAS		0
    36. 

  36. #endif
    37. 

  37. 

  38. /*
    39. 

  39.  * Memory spaces:
    40. 

  40.  */
    41. 

  41. #define T2_CONF		        (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
    42. 

  42. #define T2_IO			(IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
    43. 

  43. #define T2_SPARSE_MEM		(IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
    44. 

  44. #define T2_DENSE_MEM	        (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
    45. 

  45. 

  46. #define T2_IOCSR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
    47. 

  47. #define T2_CERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
    48. 

  48. #define T2_CERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
    49. 

  49. #define T2_CERR3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
    50. 

  50. #define T2_PERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
    51. 

  51. #define T2_PERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
    52. 

  52. #define T2_PSCR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
    53. 

  53. #define T2_HAE_1		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
    54. 

  54. #define T2_HAE_2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
    55. 

  55. #define T2_HBASE		(IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
    56. 

  56. #define T2_WBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
    57. 

  57. #define T2_WMASK1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
    58. 

  58. #define T2_TBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
    59. 

  59. #define T2_WBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
    60. 

  60. #define T2_WMASK2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
    61. 

  61. #define T2_TBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
    62. 

  62. #define T2_TLBBR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
    63. 

  63. #define T2_IVR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
    64. 

  64. #define T2_HAE_3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
    65. 

  65. #define T2_HAE_4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
    66. 

  66. 

  67. /* The CSRs below are T3/T4 only */
    68. 

  68. #define T2_WBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
    69. 

  69. #define T2_WMASK3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
    70. 

  70. #define T2_TBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
    71. 

  71. 

  72. #define T2_TDR0			(IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
    73. 

  73. #define T2_TDR1			(IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
    74. 

  74. #define T2_TDR2			(IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
    75. 

  75. #define T2_TDR3			(IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
    76. 

  76. #define T2_TDR4			(IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
    77. 

  77. #define T2_TDR5			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
    78. 

  78. #define T2_TDR6			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
    79. 

  79. #define T2_TDR7			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
    80. 

  80. 

  81. #define T2_WBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
    82. 

  82. #define T2_WMASK4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
    83. 

  83. #define T2_TBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
    84. 

  84. 

  85. #define T2_AIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
    86. 

  86. #define T2_VAR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
    87. 

  87. #define T2_DIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
    88. 

  88. #define T2_ICE			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
    89. 

  89. 

  90. #ifndef T2_ONE_HAE_WINDOW
    91. 

  91. #define T2_HAE_ADDRESS		T2_HAE_1
    92. 

  92. #endif
    93. 

  93. 

  94. /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
    95. 

  95.  3.8fff.ffff
    96. 

  96.  *
    97. 

  97.  *  +--------------+ 3 8000 0000
    98. 

  98.  *  | CPU 0 CSRs   |
    99. 

  99.  *  +--------------+ 3 8100 0000
    100. 

  100.  *  | CPU 1 CSRs   |
    101. 

  101.  *  +--------------+ 3 8200 0000
    102. 

  102.  *  | CPU 2 CSRs   |
    103. 

  103.  *  +--------------+ 3 8300 0000
    104. 

  104.  *  | CPU 3 CSRs   |
    105. 

  105.  *  +--------------+ 3 8400 0000
    106. 

  106.  *  | CPU Reserved |
    107. 

  107.  *  +--------------+ 3 8700 0000
    108. 

  108.  *  | Mem Reserved |
    109. 

  109.  *  +--------------+ 3 8800 0000
    110. 

  110.  *  | Mem 0 CSRs   |
    111. 

  111.  *  +--------------+ 3 8900 0000
    112. 

  112.  *  | Mem 1 CSRs   |
    113. 

  113.  *  +--------------+ 3 8a00 0000
    114. 

  114.  *  | Mem 2 CSRs   |
    115. 

  115.  *  +--------------+ 3 8b00 0000
    116. 

  116.  *  | Mem 3 CSRs   |
    117. 

  117.  *  +--------------+ 3 8c00 0000
    118. 

  118.  *  | Mem Reserved |
    119. 

  119.  *  +--------------+ 3 8e00 0000
    120. 

  120.  *  | PCI Bridge   |
    121. 

  121.  *  +--------------+ 3 8f00 0000
    122. 

  122.  *  | Expansion IO |
    123. 

  123.  *  +--------------+ 3 9000 0000
    124.