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connectionSignalSlot.h

connectionSignalSlot.h 53 KB
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  1. /*
    2. 

  2.  * Copyright 2007-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF522_H
    8. 

  8. #define _DEF_BF522_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* ==== begin from defBF534.h ==== */
    15. 

  15. 

  16. /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
    17. 

  17. #define PLL_CTL				0xFFC00000	/* PLL Control Register						*/
    18. 

  18. #define PLL_DIV				0xFFC00004	/* PLL Divide Register						*/
    19. 

  19. #define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register		*/
    20. 

  20. #define PLL_STAT			0xFFC0000C	/* PLL Status Register						*/
    21. 

  21. #define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register					*/
    22. 

  22. #define CHIPID        0xFFC00014  /* Device ID Register */
    23. 

  23. 

  24. 

  25. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
    26. 

  26. #define SWRST				0xFFC00100	/* Software Reset Register					*/
    27. 

  27. #define SYSCR				0xFFC00104	/* System Configuration Register			*/
    28. 

  28. #define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register	*/
    29. 

  29. 

  30. #define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register					*/
    31. 

  31. #define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0			*/
    32. 

  32. #define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1			*/
    33. 

  33. #define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2			*/
    34. 

  34. #define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3			*/
    35. 

  35. #define SIC_ISR0				0xFFC00120	/* Interrupt Status Register				*/
    36. 

  36. #define SIC_IWR0				0xFFC00124	/* Interrupt Wakeup Register				*/
    37. 

  37. 

  38. /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
    39. 

  39. #define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
    40. 

  40. #define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
    41. 

  41. #define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
    42. 

  42. #define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
    43. 

  43. #define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
    44. 

  44. #define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
    45. 

  45. #define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
    46. 

  46. 

  47. 

  48. /* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
    49. 

  49. #define WDOG_CTL			0xFFC00200	/* Watchdog Control Register				*/
    50. 

  50. #define WDOG_CNT			0xFFC00204	/* Watchdog Count Register					*/
    51. 

  51. #define WDOG_STAT			0xFFC00208	/* Watchdog Status Register					*/
    52. 

  52. 

  53. 

  54. /* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
    55. 

  55. #define RTC_STAT			0xFFC00300	/* RTC Status Register						*/
    56. 

  56. #define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register			*/
    57. 

  57. #define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register			*/
    58. 

  58. #define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register				*/
    59. 

  59. #define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register					*/
    60. 

  60. #define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register			*/
    61. 

  61. #define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro		*/
    62. 

  62. 

  63. 

  64. /* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
    65. 

  65. #define UART0_THR			0xFFC00400	/* Transmit Holding register				*/
    66. 

  66. #define UART0_RBR			0xFFC00400	/* Receive Buffer register					*/
    67. 

  67. #define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)					*/
    68. 

  68. #define UART0_IER			0xFFC00404	/* Interrupt Enable Register				*/
    69. 

  69. #define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)				*/
    70. 

  70. #define UART0_IIR			0xFFC00408	/* Interrupt Identification Register		*/
    71. 

  71. #define UART0_LCR			0xFFC0040C	/* Line Control Register					*/
    72. 

  72. #define UART0_MCR			0xFFC00410	/* Modem Control Register					*/
    73. 

  73. #define UART0_LSR			0xFFC00414	/* Line Status Register						*/
    74. 

  74. #define UART0_MSR			0xFFC00418	/* Modem Status Register					*/
    75. 

  75. #define UART0_SCR			0xFFC0041C	/* SCR Scratch Register						*/
    76. 

  76. #define UART0_GCTL			0xFFC00424	/* Global Control Register					*/
    77. 

  77. 

  78. 

  79. /* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/
    80. 

  80. #define SPI0_REGBASE			0xFFC00500
    81. 

  81. #define SPI_CTL				0xFFC00500	/* SPI Control Register						*/
    82. 

  82. #define SPI_FLG				0xFFC00504	/* SPI Flag register						*/
    83. 

  83. #define SPI_STAT			0xFFC00508	/* SPI Status register						*/
    84. 

  84. #define SPI_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register		*/
    85. 

  85. #define SPI_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register			*/
    86. 

  86. #define SPI_BAUD			0xFFC00514	/* SPI Baud rate Register					*/
    87. 

  87. #define SPI_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register					*/
    88. 

  88. 

  89. 

  90. /* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
    91. 

  91. #define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register			*/
    92. 

  92. #define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register					*/
    93. 

  93. #define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register					*/
    94. 

  94. #define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register					*/
    95. 

  95. 

  96. #define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register  			*/
    97. 

  97. #define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register        			*/
    98. 

  98. #define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register         			*/
    99. 

  99. #define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register          			*/
    100. 

  100. 

  101. #define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register  			*/
    102. 

  102. #define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register        			*/
    103. 

  103. #define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register         			*/
    104. 

  104. #define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register          			*/
    105. 

  105. 

  106. #define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register			*/
    107. 

  107. #define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register					*/
    108. 

  108. #define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register					*/
    109. 

  109. #define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register					*/
    110. 

  110. 

  111. #define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register  			*/
    112. 

  112. #define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register        			*/
    113. 

  113. #define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register         			*/
    114. 

  114. #define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register          			*/
    115. 

  115. 

  116. #define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register  			*/
    117. 

  117. #define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register        			*/
    118. 

  118. #define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register         			*/
    119. 

  119. #define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register          			*/
    120. 

  120. 

  121. #define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register  			*/
    122. 

  122. #define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register        			*/
    123. 

  123. #define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register         			*/
    124. 

  124. #define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register          			*/
    125. 

  125. 

  126. #define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register  			*/
    127. 

  127. #define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register        			*/
    128. 

  128. #define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register         			*/
    129. 

  129. #define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/
    130. 

  130. 

  131. #define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register					*/
    132. 

  132. #define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register					*/
    133. 

  133. #define TIMER_STATUS		0xFFC00688	/* Timer Status Register					*/
    134. 

  134. 

  135. 

  136. /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)												*/
    137. 

  137. #define PORTFIO					0xFFC00700	/* Port F I/O Pin State Specify Register				*/
    138. 

  138. #define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register		*/
    139. 

  139. #define PORTFIO_SET				0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register			*/
    140. 

  140. #define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
    141. 

  141. #define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register	*/
    142. 

  142. #define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register			*/
    143. 

  143. #define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register			*/
    144. 

  144. #define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register	*/
    145. 

  145. #define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register	*/
    146. 

  146. #define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register			*/
    147. 

  147. #define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register			*/
    148. 

  148. #define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register	*/
    149. 

  149. #define PORTFIO_DIR				0xFFC00730	/* Port F I/O Direction Register						*/
    150. 

  150. #define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
    151. 

  151. #define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register				*/
    152. 

  152. #define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register				*/
    153. 

  153. #define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
    154. 

  154. 

  155. 

  156. /* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)										*/
    157. 

  157. #define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register			*/
    158. 

  158. #define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register			*/
    159. 

  159. #define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider					*/
    160. 

  160. #define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider				*/
    161. 

  161. #define SPORT0_TX			0xFFC00810	/* SPORT0 TX Data Register							*/
    162. 

  162. #define SPORT0_RX			0xFFC00818	/* SPORT0 RX Data Register							*/
    163. 

  163. #define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register			*/
    164. 

  164. #define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register			*/
    165. 

  165. #define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider						*/
    166. 

  166. #define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider				*/
    167. 

  167. #define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
    168. 

  168. #define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register					*/
    169. 

  169. #define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1	*/
    170. 

  170. #define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2	*/
    171. 

  171. #define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0	*/
    172. 

  172. #define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1	*/
    173. 

  173. #define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2	*/
    174. 

  174. #define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3	*/
    175. 

  175. #define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0	*/
    176. 

  176. #define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1	*/
    177. 

  177. #define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2	*/
    178. 

  178. #define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3	*/
    179. 

  179. 

  180. 

  181. /* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)										*/
    182. 

  182. #define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register			*/
    183. 

  183. #define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register			*/
    184. 

  184. #define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider					*/
    185. 

  185. #define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider				*/
    186. 

  186. #define SPORT1_TX			0xFFC00910	/* SPORT1 TX Data Register							*/
    187. 

  187. #define SPORT1_RX			0xFFC00918	/* SPORT1 RX Data Register							*/
    188. 

  188. #define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register			*/
    189. 

  189. #define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register			*/
    190. 

  190. #define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider						*/
    191. 

  191. #define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider				*/
    192. 

  192. #define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
    193. 

  193. #define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register					*/
    194. 

  194. #define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1	*/
    195. 

  195. #define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2	*/
    196. 

  196. #define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0	*/
    197. 

  197. #define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1	*/
    198. 

  198. #define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2	*/
    199. 

  199. #define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3	*/
    200. 

  200. #define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0	*/
    201. 

  201. #define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1	*/
    202. 

  202. #define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2	*/
    203. 

  203. #define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3	*/
    204. 

  204. 

  205. 

  206. /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)								*/
    207. 

  207. #define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register	*/
    208. 

  208. #define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0	*/
    209. 

  209. #define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1	*/
    210. 

  210. #define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register				*/
    211. 

  211. #define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register					*/
    212. 

  212. #define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register			*/
    213. 

  213. #define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register						*/
    214. 

  214. 

  215. 

  216. /* DMA Traffic Control Registers													*/
    217. 

  217. #define DMAC_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
    218. 

  218. #define DMAC_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
    219. 

  219. 

  220. /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/
    221. 

  221. #define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/
    222. 

  222. #define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
    223. 

  223. #define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
    224. 

  224. #define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
    225. 

  225. #define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
    226. 

  226. #define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
    227. 

  227. #define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
    228. 

  228. #define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register	*/
    229. 

  229. #define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register				*/
    230. 

  230. #define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
    231. 

  231. #define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register				*/
    232. 

  232. #define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register				*/
    233. 

  233. #define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register				*/
    234. 

  234. 

  235. #define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register		*/
    236. 

  236. #define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
    237. 

  237. #define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
    238. 

  238. #define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
    239. 

  239. #define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
    240. 

  240. #define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
    241. 

  241. #define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
    242. 

  242. #define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register	*/
    243. 

  243. #define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register				*/
    244. 

  244. #define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
    245. 

  245. #define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register				*/
    246. 

  246. #define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register				*/
    247. 

  247. #define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register				*/
    248. 

  248. 

  249. #define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register		*/
    250. 

  250. #define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
    251. 

  251. #define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
    252. 

  252. #define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
    253. 

  253. #define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
    254. 

  254. #define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
    255. 

  255. #define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
    256. 

  256. #define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register	*/
    257. 

  257. #define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register				*/
    258. 

  258. #define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
    259. 

  259. #define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register				*/
    260. 

  260. #define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register				*/
    261. 

  261. #define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register				*/
    262. 

  262. 

  263. #define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register		*/
    264. 

  264. #define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
    265. 

  265. #define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
    266. 

  266. #define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
    267. 

  267. #define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
    268. 

  268. #define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
    269. 

  269. #define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
    270. 

  270. #define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register	*/
    271. 

  271. #define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register				*/
    272. 

  272. #define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
    273. 

  273. #define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register				*/
    274. 

  274. #define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register				*/
    275. 

  275. #define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register				*/
    276. 

  276. 

  277. #define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register		*/
    278. 

  278. #define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
    279. 

  279. #define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
    280. 

  280. #define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
    281. 

  281. #define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
    282. 

  282. #define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
    283. 

  283. #define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
    284. 

  284. #define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register	*/
    285. 

  285. #define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register				*/
    286. 

  286. #define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
    287. 

  287. #define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register				*/
    288. 

  288. #define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register				*/
    289. 

  289. #define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register				*/
    290. 

  290. 

  291. #define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register		*/
    292. 

  292. #define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
    293. 

  293. #define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
    294. 

  294. #define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
    295. 

  295. #define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
    296. 

  296. #define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
    297. 

  297. #define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
    298. 

  298. #define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register	*/
    299. 

  299. #define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register				*/
    300. 

  300. #define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
    301. 

  301. #define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register				*/
    302. 

  302. #define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register				*/
    303. 

  303. #define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register				*/
    304. 

  304. 

  305. #define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register		*/
    306. 

  306. #define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
    307. 

  307. #define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
    308. 

  308. #define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
    309. 

  309. #define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
    310. 

  310. #define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
    311. 

  311. #define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
    312. 

  312. #define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register	*/
    313. 

  313. #define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register				*/
    314. 

  314. #define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
    315. 

  315. #define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register				*/
    316. 

  316. #define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register				*/
    317. 

  317. #define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register				*/
    318. 

  318. 

  319. #define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register		*/
    320. 

  320. #define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
    321. 

  321. #define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
    322. 

  322. #define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
    323. 

  323. #define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
    324. 

  324. #define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
    325. 

  325. #define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
    326. 

  326. #define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register	*/
    327. 

  327. #define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register				*/
    328. 

  328. #define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
    329. 

  329. #define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register				*/
    330. 

  330. #define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register				*/
    331. 

  331. #define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register				*/
    332. 

  332. 

  333. #define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
    334. 

  334. #define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
    335. 

  335. #define DMA8_CONFIG				0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
    336. 

  336. #define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
    337. 

  337. #define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
    338. 

  338. #define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
    339. 

  339. #define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
    340. 

  340. #define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
    341. 

  341. #define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register				*/
    342. 

  342. #define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
    343. 

  343. #define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register				*/
    344. 

  344. #define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register				*/
    345. 

  345. #define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register				*/
    346. 

  346. 

  347. #define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
    348. 

  348. #define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register					*/
    349. 

  349. #define DMA9_CONFIG				0xFFC00E48	/* DMA Channel 9 Configuration Register					*/
    350. 

  350. #define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register						*/
    351. 

  351. #define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register						*/
    352. 

  352. #define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register						*/
    353. 

  353. #define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register						*/
    354. 

  354. #define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
    355. 

  355. #define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register				*/
    356. 

  356. #define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register				*/
    357. 

  357. #define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register				*/
    358. 

  358. #define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register				*/
    359. 

  359. #define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register				*/
    360. 

  360. 

  361. #define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
    362. 

  362. #define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register				*/
    363. 

  363. #define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register				*/
    364. 

  364. #define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register						*/
    365. 

  365. #define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register						*/
    366. 

  366. #define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register						*/
    367. 

  367. #define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register						*/
    368. 

  368. #define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
    369. 

  369. #define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register				*/
    370. 

  370. #define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register				*/
    371. 

  371. #define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register				*/
    372. 

  372. #define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register				*/
    373. 

  373. #define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register				*/
    374. 

  374. 

  375. #define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
    376. 

  376. #define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register				*/
    377. 

  377. #define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register				*/
    378. 

  378. #define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register						*/
    379. 

  379. #define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register						*/
    380. 

  380. #define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register						*/
    381. 

  381. #define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register						*/
    382. 

  382. #define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
    383. 

  383. #define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register				*/
    384. 

  384. #define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register				*/
    385. 

  385. #define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register				*/
    386. 

  386. #define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register				*/
    387. 

  387. #define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register				*/
    388. 

  388. 

  389. #define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register		*/
    390. 

  390. #define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register				*/
    391. 

  391. #define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register				*/
    392. 

  392. #define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register						*/
    393. 

  393. #define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register					*/
    394. 

  394. #define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register						*/
    395. 

  395. #define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register					*/
    396. 

  396. #define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register	*/
    397. 

  397. #define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register				*/
    398. 

  398. #define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register			*/
    399. 

  399. #define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register				*/
    400. 

  400. #define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register				*/
    401. 

  401. #define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register				*/
    402. 

  402. 

  403. #define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register			*/
    404. 

  404. #define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register					*/
    405. 

  405. #define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register					*/
    406. 

  406. #define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register							*/
    407. 

  407. #define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register							*/
    408. 

  408. #define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register							*/
    409. 

  409. #define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register							*/
    410. 

  410. #define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register		*/
    411. 

  411. #define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register					*/
    412. 

  412. #define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register					*/
    413. 

  413. #define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register					*/
    414. 

  414. #define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register					*/
    415. 

  415. #define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register					*/
    416. 

  416. 

  417. #define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register		*/
    418. 

  418. #define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register				*/
    419. 

  419. #define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register				*/
    420. 

  420. #define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register						*/
    421. 

  421. #define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register					*/
    422. 

  422. #define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register						*/
    423. 

  423. #define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register					*/
    424. 

  424. #define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register	*/
    425. 

  425. #define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register				*/
    426. 

  426. #define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register			*/
    427. 

  427. #define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register				*/
    428. 

  428. #define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register				*/
    429. 

  429. #define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register				*/
    430. 

  430. 

  431. #define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register			*/
    432. 

  432. #define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register					*/
    433. 

  433. #define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register					*/
    434. 

  434. #define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register							*/
    435. 

  435. #define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register							*/
    436. 

  436. #define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register							*/
    437. 

  437. #define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register							*/
    438. 

  438. #define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register		*/
    439. 

  439. #define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register					*/
    440. 

  440. #define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register					*/
    441. 

  441. #define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register					*/
    442. 

  442. #define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register					*/
    443. 

  443. #define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register					*/
    444. 

  444. 

  445. 

  446. /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)				*/
    447. 

  447. #define PPI_CONTROL			0xFFC01000	/* PPI Control Register			*/
    448. 

  448. #define PPI_STATUS			0xFFC01004	/* PPI Status Register			*/
    449. 

  449. #define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register	*/
    450. 

  450. #define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register		*/
    451. 

  451. #define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register	*/
    452. 

  452. 

  453. 

  454. /* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
    455. 

  455. #define TWI0_REGBASE			0xFFC01400
    456. 

  456. #define TWI0_CLKDIV			0xFFC01400	/* Serial Clock Divider Register			*/
    457. 

  457. #define TWI0_CONTROL			0xFFC01404	/* TWI Control Register						*/
    458. 

  458. #define TWI0_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register				*/
    459. 

  459. #define TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register				*/
    460. 

  460. #define TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register				*/
    461. 

  461. #define TWI0_MASTER_CTL		0xFFC01414	/* Master Mode Control Register				*/
    462. 

  462. #define TWI0_MASTER_STAT		0xFFC01418	/* Master Mode Status Register				*/
    463. 

  463. #define TWI0_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register				*/
    464. 

  464. #define TWI0_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register			*/
    465. 

  465. #define TWI0_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register		*/
    466. 

  466. #define TWI0_FIFO_CTL		0xFFC01428	/* FIFO Control Register					*/
    467. 

  467. #define TWI0_FIFO_STAT		0xFFC0142C	/* FIFO Status Register						*/
    468. 

  468. #define TWI0_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register	*/
    469. 

  469. #define TWI0_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register	*/
    470. 

  470. #define TWI0_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register	*/
    471. 

  471. #define TWI0_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register	*/
    472. 

  472. 

  473. 

  474. /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)												*/
    475. 

  475. #define PORTGIO					0xFFC01500	/* Port G I/O Pin State Specify Register				*/
    476. 

  476. #define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register		*/
    477. 

  477. #define PORTGIO_SET				0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register			*/
    478. 

  478. #define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register					*/
    479. 

  479. #define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register	*/
    480. 

  480. #define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register			*/
    481. 

  481. #define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register			*/
    482. 

  482. #define PORTGIO_MASKA_TOGGLE	0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register	*/
    483. 

  483. #define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register	*/
    484. 

  484. #define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register			*/
    485. 

  485. #define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register			*/
    486. 

  486. #define PORTGIO_MASKB_TOGGLE	0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register	*/
    487. 

  487. #define PORTGIO_DIR				0xFFC01530	/* Port G I/O Direction Register						*/
    488. 

  488. #define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register					*/
    489. 

  489. #define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register				*/
    490. 

  490. #define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register				*/
    491. 

  491. #define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register						*/
    492. 

  492. 

  493. 

  494. /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)												*/
    495. 

  495. #define PORTHIO					0xFFC01700	/* Port H I/O Pin State Specify Register				*/
    496. 

  496. #define PORTHIO_CLEAR			0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register		*/
    497. 

  497. #define PORTHIO_SET				0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register			*/
    498. 

  498. #define PORTHIO_TOGGLE			0xFFC0170C	/* Port H I/O Pin State Toggle Register					*/
    499. 

  499. #define PORTHIO_MASKA			0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register	*/
    500. 

  500. #define PORTHIO_MASKA_CLEAR		0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register			*/
    501. 

  501. #define PORTHIO_MASKA_SET		0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register			*/
    502. 

  502. #define PORTHIO_MASKA_TOGGLE	0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register	*/
    503. 

  503. #define PORTHIO_MASKB			0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register	*/
    504. 

  504. #define PORTHIO_MASKB_CLEAR		0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register			*/
    505. 

  505. #define PORTHIO_MASKB_SET		0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register			*/
    506. 

  506. #define PORTHIO_MASKB_TOGGLE	0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register	*/
    507. 

  507. #define PORTHIO_DIR				0xFFC01730	/* Port H I/O Direction Register						*/
    508. 

  508. #define PORTHIO_POLAR			0xFFC01734	/* Port H I/O Source Polarity Register					*/
    509. 

  509. #define PORTHIO_EDGE			0xFFC01738	/* Port H I/O Source Sensitivity Register				*/
    510. 

  510. #define PORTHIO_BOTH			0xFFC0173C	/* Port H I/O Set on BOTH Edges Register				*/
    511. 

  511. #define PORTHIO_INEN			0xFFC01740	/* Port H I/O Input Enable Register						*/
    512. 

  512. 

  513. 

  514. /* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
    515. 

  515. #define UART1_THR			0xFFC02000	/* Transmit Holding register			*/
    516. 

  516. #define UART1_RBR			0xFFC02000	/* Receive Buffer register				*/
    517. 

  517. #define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)				*/
    518. 

  518. #define UART1_IER			0xFFC02004	/* Interrupt Enable Register			*/
    519. 

  519. #define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)			*/
    520. 

  520. #define UART1_IIR			0xFFC02008	/* Interrupt Identification Register	*/
    521. 

  521. #define UART1_LCR			0xFFC0200C	/* Line Control Register				*/
    522. 

  522. #define UART1_MCR			0xFFC02010	/* Modem Control Register				*/
    523. 

  523. #define UART1_LSR			0xFFC02014	/* Line Status Register					*/
    524. 

  524. #define UART1_MSR			0xFFC02018	/* Modem Status Register				*/
    525. 

  525. #define UART1_SCR			0xFFC0201C	/* SCR Scratch Register					*/
    526. 

  526. #define UART1_GCTL			0xFFC02024	/* Global Control Register				*/
    527. 

  527. 

  528. 

  529. /* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
    530. 

  530. 

  531. /* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)											*/
    532. 

  532. #define PORTF_FER			0xFFC03200	/* Port F Function Enable Register (Alternate/Flag*)	*/
    533. 

  533. #define PORTG_FER			0xFFC03204	/* Port G Function Enable Register (Alternate/Flag*)	*/
    534. 

  534. #define PORTH_FER			0xFFC03208	/* Port H Function Enable Register (Alternate/Flag*)	*/
    535. 

  535. #define BFIN_PORT_MUX			0xFFC0320C	/* Port Multiplexer Control Register					*/
    536. 

  536. 

  537. 

  538. /* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)										*/
    539. 

  539. #define HMDMA0_CONTROL		0xFFC03300	/* Handshake MDMA0 Control Register					*/
    540. 

  540. #define HMDMA0_ECINIT		0xFFC03304	/* HMDMA0 Initial Edge Count Register				*/
    541. 

  541. #define HMDMA0_BCINIT		0xFFC03308	/* HMDMA0 Initial Block Count Register				*/
    542. 

  542. #define HMDMA0_ECURGENT		0xFFC0330C	/* HMDMA0 Urgent Edge Count Threshold Register		*/
    543. 

  543. #define HMDMA0_ECOVERFLOW	0xFFC03310	/* HMDMA0 Edge Count Overflow Interrupt Register	*/
    544. 

  544. #define HMDMA0_ECOUNT		0xFFC03314	/* HMDMA0 Current Edge Count Register				*/
    545. 

  545. #define HMDMA0_BCOUNT		0xFFC03318	/* HMDMA0 Current Block Count Register				*/
    546. 

  546. 

  547. #define HMDMA1_CONTROL		0xFFC03340	/* Handshake MDMA1 Control Register					*/
    548. 

  548. #define HMDMA1_ECINIT		0xFFC03344	/* HMDMA1 Initial Edge Count Register				*/
    549. 

  549. #define HMDMA1_BCINIT		0xFFC03348	/* HMDMA1 Initial Block Count Register				*/
    550. 

  550. #define HMDMA1_ECURGENT		0xFFC0334C	/* HMDMA1 Urgent Edge Count Threshold Register		*/
    551. 

  551. #define HMDMA1_ECOVERFLOW	0xFFC03350	/* HMDMA1 Edge Count Overflow Interrupt Register	*/
    552. 

  552. #define HMDMA1_ECOUNT		0xFFC03354	/* HMDMA1 Current Edge Count Register				*/
    553. 

  553. #define HMDMA1_BCOUNT		0xFFC03358	/* HMDMA1 Current Block Count Register				*/
    554. 

  554. 

  555. /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
    556. 

  556. #define PORTF_MUX               0xFFC03210      /* Port F mux control */
    557. 

  557. #define PORTG_MUX               0xFFC03214      /* Port G mux control */
    558. 

  558. #define PORTH_MUX               0xFFC03218      /* Port H mux control */
    559. 

  559. #define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
    560. 

  560. #define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
    561. 

  561. #define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
    562. 

  562. #define PORTF_SLEW              0xFFC03230      /* Port F slew control */
    563. 

  563. #define PORTG_SLEW              0xFFC03234      /* Port G slew control */
    564. 

  564. #define PORTH_SLEW              0xFFC03238      /* Port H slew control */
    565. 

  565. #define PORTF_HYSTERESIS        0xFFC03240      /* Port F Schmitt trigger control */
    566. 

  566. #define PORTG_HYSTERESIS        0xFFC03244      /* Port G Schmitt trigger control */
    567. 

  567. #define PORTH_HYSTERESIS        0xFFC03248      /* Port H Schmitt trigger control */
    568. 

  568. #define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
    569. 

  569. #define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
    570. 

  570. #define MISCPORT_HYSTERESIS     0xFFC03288      /* Misc Port Schmitt trigger control */
    571. 

  571. 

  572. 

  573. /***********************************************************************************
    574. 

  574. ** System MMR Register Bits And Macros
    575. 

  575. **
    576. 

  576. ** Disclaimer:	All macros are intended to make C and Assembly code more readable.
    577. 

  577. **				Use these macros carefully, as any that do left shifts for field
    578. 

  578. **				depositing will result in the lower order bits being destroyed.  Any
    579. 

  579. **				macro that shifts left to properly position the bit-field should be
    580. 

  580. **				used as part of an OR to initialize a register and NOT as a dynamic
    581. 

  581. **				modifier UNLESS the lower order bits are saved and ORed back in when
    582. 

  582. **				the macro is used.
    583. 

  583. *************************************************************************************/
    584. 

  584. 

  585. /* CHIPID Masks */
    586. 

  586. #define CHIPID_VERSION         0xF0000000
    587. 

  587. #define CHIPID_FAMILY          0x0FFFF000
    588. 

  588. #define CHIPID_MANUFACTURE     0x00000FFE
    589. 

  589. 

  590. /* SWRST Masks																		*/
    591. 

  591. #define SYSTEM_RESET		0x0007	/* Initiates A System Software Reset			*/
    592. 

  592. #define	DOUBLE_FAULT		0x0008	/* Core Double Fault Causes Reset				*/
    593. 

  593. #define RESET_DOUBLE		0x2000	/* SW Reset Generated By Core Double-Fault		*/
    594. 

  594. #define RESET_WDOG			0x4000	/* SW Reset Generated By Watchdog Timer			*/
    595. 

  595. #define RESET_SOFTWARE		0x8000	/* SW Reset Occurred Since Last Read Of SWRST	*/
    596. 

  596. 

  597. /* SYSCR Masks																				*/
    598. 

  598. #define BMODE				0x0007	/* Boot Mode - Latched During HW Reset From Mode Pins	*/
    599. 

  599. #define	NOBOOT				0x0010	/* Execute From L1 or ASYNC Bank 0 When BMODE = 0		*/
    600. 

  600. 

  601. 

  602. /* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
    603. 

  603. /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK										*/
    604. 

  604. 

  605. #if 0
    606. 

  606. #define IRQ_PLL_WAKEUP	0x00000001	/* PLL Wakeup Interrupt			 					*/
    607. 

  607. 

  608. #define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
    609. 

  609. #define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
    610. 

  610. #define IRQ_RTC			0x00000008	/* Real Time Clock Interrupt 						*/
    611. 

  611. #define IRQ_DMA0		0x00000010	/* DMA Channel 0 (PPI) Interrupt 					*/
    612. 

  612. #define IRQ_DMA3		0x00000020	/* DMA Channel 3 (SPORT0 RX) Interrupt 				*/
    613. 

  613. #define IRQ_DMA4		0x00000040	/* DMA Channel 4 (SPORT0 TX) Interrupt 				*/
    614. 

  614. #define IRQ_DMA5		0x00000080	/* DMA Channel 5 (SPORT1 RX) Interrupt 				*/
    615. 

  615. 

  616. #define IRQ_DMA6		0x00000100	/* DMA Channel 6 (SPORT1 TX) Interrupt 		 		*/
    617. 

  617. #define IRQ_TWI			0x00000200	/* TWI Interrupt									*/
    618. 

  618. #define IRQ_DMA7		0x00000400	/* DMA Channel 7 (SPI) Interrupt 					*/
    619. 

  619. #define IRQ_DMA8		0x00000800	/* DMA Channel 8 (UART0 RX) Interrupt 				*/
    620. 

  620. #define IRQ_DMA9		0x00001000	/* DMA Channel 9 (UART0 TX) Interrupt 				*/
    621. 

  621. #define IRQ_DMA10		0x00002000	/* DMA Channel 10 (UART1 RX) Interrupt 				*/
    622. 

  622. #define IRQ_DMA11		0x00004000	/* DMA Channel 11 (UART1 TX) Interrupt 				*/
    623. 

  623. #define IRQ_CAN_RX		0x00008000	/* CAN Receive Interrupt 							*/
    624. 

  624. 

  625. #define IRQ_CAN_TX		0x00010000	/* CAN Transmit Interrupt  							*/
    626. 

  626. #define IRQ_DMA1		0x00020000	/* DMA Channel 1 (Ethernet RX) Interrupt 			*/
    627. 

  627. #define IRQ_PFA_PORTH	0x00020000	/* PF Port H (PF47:32) Interrupt A 					*/
    628. 

  628. #define IRQ_DMA2		0x00040000	/* DMA Channel 2 (Ethernet TX) Interrupt 			*/
    629. 

  629. #define IRQ_PFB_PORTH	0x00040000	/* PF Port H (PF47:32) Interrupt B 					*/
    630. 

  630. #define IRQ_TIMER0		0x00080000	/* Timer 0 Interrupt								*/
    631. 

  631. #define IRQ_TIMER1		0x00100000	/* Timer 1 Interrupt 								*/
    632. 

  632. #define IRQ_TIMER2		0x00200000	/* Timer 2 Interrupt 								*/
    633. 

  633. #define IRQ_TIMER3		0x00400000	/* Timer 3 Interrupt 								*/
    634. 

  634. #define IRQ_TIMER4		0x00800000	/* Timer 4 Interrupt 								*/
    635. 

  635. 

  636. #define IRQ_TIMER5		0x01000000	/* Timer 5 Interrupt 								*/
    637. 

  637. #define IRQ_TIMER6		0x02000000	/* Timer 6 Interrupt 								*/
    638. 

  638. #define IRQ_TIMER7		0x04000000	/* Timer 7 Interrupt 								*/
    639. 

  639. #define IRQ_PFA_PORTFG	0x08000000	/* PF Ports F&G (PF31:0) Interrupt A 				*/
    640. 

  640. #define IRQ_PFB_PORTF	0x80000000	/* PF Port F (PF15:0) Interrupt B 					*/
    641. 

  641. #define IRQ_DMA12		0x20000000	/* DMA Channels 12 (MDMA1 Source) RX Interrupt 		*/
    642. 

  642. #define IRQ_DMA13		0x20000000	/* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
    643. 

  643. #define IRQ_DMA14		0x40000000	/* DMA Channels 14 (MDMA0 Source) RX Interrupt 		*/
    644. 

  644. #define IRQ_DMA15		0x40000000	/* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
    645. 

  645. #define IRQ_WDOG		0x80000000	/* Software Watchdog Timer Interrupt 				*/
    646. 

  646. #define IRQ_PFB_PORTG	0x10000000	/* PF Port G (PF31:16) Interrupt B 					*/
    647. 

  647. #endif
    648. 

  648. 

  649. /* SIC_IAR0 Macros															*/
    650. 

  650. #define P0_IVG(x)		(((x)&0xF)-7)			/* Peripheral #0 assigned IVG #x 	*/
    651. 

  651. #define P1_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #1 assigned IVG #x 	*/
    652. 

  652. #define P2_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #2 assigned IVG #x 	*/
    653. 

  653. #define P3_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #3 assigned IVG #x	*/
    654. 

  654. #define P4_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #4 assigned IVG #x	*/
    655. 

  655. #define P5_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #5 assigned IVG #x	*/
    656. 

  656. #define P6_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #6 assigned IVG #x	*/
    657. 

  657. #define P7_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #7 assigned IVG #x	*/
    658. 

  658. 

  659. /* SIC_IAR1 Macros															*/
    660. 

  660. #define P8_IVG(x)		(((x)&0xF)-7)			/* Peripheral #8 assigned IVG #x 	*/
    661. 

  661. #define P9_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #9 assigned IVG #x 	*/
    662. 

  662. #define P10_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #10 assigned IVG #x	*/
    663. 

  663. #define P11_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #11 assigned IVG #x 	*/
    664. 

  664. #define P12_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #12 assigned IVG #x	*/
    665. 

  665. #define P13_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #13 assigned IVG #x	*/
    666. 

  666. #define P14_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #14 assigned IVG #x	*/
    667. 

  667. #define P15_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #15 assigned IVG #x	*/
    668. 

  668. 

  669. /* SIC_IAR2 Macros															*/
    670. 

  670. #define P16_IVG(x)		(((x)&0xF)-7)			/* Peripheral #16 assigned IVG #x	*/
    671. 

  671. #define P17_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #17 assigned IVG #x	*/
    672. 

  672. #define P18_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #18 assigned IVG #x	*/
    673. 

  673. #define P19_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #19 assigned IVG #x	*/
    674. 

  674. #define P20_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #20 assigned IVG #x	*/
    675. 

  675. #define P21_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #21 assigned IVG #x	*/
    676. 

  676. #define P22_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #22 assigned IVG #x	*/
    677. 

  677. #define P23_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #23 assigned IVG #x	*/
    678. 

  678. 

  679. /* SIC_IAR3 Macros															*/
    680. 

  680. #define P24_IVG(x)		(((x)&0xF)-7)			/* Peripheral #24 assigned IVG #x	*/
    681. 

  681. #define P25_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #25 assigned IVG #x	*/
    682. 

  682. #define P26_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #26 assigned IVG #x	*/
    683. 

  683. #define P27_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #27 assigned IVG #x	*/
    684. 

  684. #define P28_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #28 assigned IVG #x	*/
    685. 

  685. #define P29_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #29 assigned IVG #x	*/
    686. 

  686. #define P30_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #30 assigned IVG #x	*/
    687. 

  687. #define P31_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #31 assigned IVG #x	*/
    688. 

  688. 

  689. 

  690. /* SIC_IMASK Masks																		*/
    691. 

  691. #define SIC_UNMASK_ALL	0x00000000					/* Unmask all peripheral interrupts	*/
    692. 

  692. #define SIC_MASK_ALL	0xFFFFFFFF					/* Mask all peripheral interrupts	*/
    693. 

  693. #define SIC_MASK(x)		(1 << ((x)&0x1F))					/* Mask Peripheral #x interrupt		*/
    694. 

  694. #define SIC_UNMASK(x)	(0xFFFFFFFF ^ (1 << ((x)&0x1F)))	/* Unmask Peripheral #x interrupt	*/
    695. 

  695. 

  696. /* SIC_IWR Masks																		*/
    697. 

  697. #define IWR_DISABLE_ALL	0x00000000					/* Wakeup Disable all peripherals	*/
    698. 

  698. #define IWR_ENABLE_ALL	0xFFFFFFFF					/* Wakeup Enable all peripherals	*/
    699. 

  699. #define IWR_ENABLE(x)	(1 << ((x)&0x1F))					/* Wakeup Enable Peripheral #x		*/
    700. 

  700. #define IWR_DISABLE(x)	(0xFFFFFFFF ^ (1 << ((x)&0x1F))) 	/* Wakeup Disable Peripheral #x		*/
    701. 

  701. 

  702. /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
    703. 

  703. /* TIMER_ENABLE Masks													*/
    704. 

  704. #define TIMEN0			0x0001		/* Enable Timer 0					*/
    705. 

  705. #define TIMEN1			0x0002		/* Enable Timer 1					*/
    706. 

  706. #define TIMEN2			0x0004		/* Enable Timer 2					*/
    707. 

  707. #define TIMEN3			0x0008		/* Enable Timer 3					*/
    708. 

  708. #define TIMEN4			0x0010		/* Enable Timer 4					*/
    709. 

  709. #define TIMEN5			0x0020		/* Enable Timer 5					*/
    710. 

  710. #define TIMEN6			0x0040		/* Enable Timer 6					*/
    711. 

  711. #define TIMEN7			0x0080		/* Enable Timer 7					*/
    712. 

  712. 

  713. /* TIMER_DISABLE Masks													*/
    714. 

  714. #define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
    715. 

  715. #define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
    716. 

  716. #define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
    717. 

  717. #define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
    718. 

  718. #define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
    719. 

  719. #define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
    720. 

  720. #define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
    721. 

  721. #define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
    722. 

  722. 

  723. /* TIMER_STATUS Masks													*/
    724. 

  724. #define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
    725. 

  725. #define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
    726. 

  726. #define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
    727. 

  727. #define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
    728. 

  728. #define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
    729. 

  729. #define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
    730. 

  730. #define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
    731. 

  731. #define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
    732. 

  732. #define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
    733. 

  733. #define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
    734. 

  734. #define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
    735. 

  735. #define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
    736. 

  736. #define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
    737. 

  737. #define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
    738. 

  738. #define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
    739. 

  739. #define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
    740. 

  740. #define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
    741. 

  741. #define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
    742. 

  742. #define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
    743. 

  743. #define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
    744. 

  744. #define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
    745. 

  745. #define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
    746. 

  746. #define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
    747. 

  747. #define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
    748. 

  748. 

  749. /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
    750. 

  750. #define TOVL_ERR0 TOVF_ERR0
    751. 

  751. #define TOVL_ERR1 TOVF_ERR1
    752. 

  752. #define TOVL_ERR2 TOVF_ERR2
    753. 

  753. #define TOVL_ERR3 TOVF_ERR3
    754. 

  754. #define TOVL_ERR4 TOVF_ERR4
    755. 

  755. #define TOVL_ERR5 TOVF_ERR5
    756. 

  756. #define TOVL_ERR6 TOVF_ERR6
    757. 

  757. #define TOVL_ERR7 TOVF_ERR7
    758. 

  758. 

  759. /* TIMERx_CONFIG Masks													*/
    760. 

  760. #define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
    761. 

  761. #define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
    762. 

  762. #define EXT_CLK			0x0003	/* External Clock Mode					*/
    763. 

  763. #define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
    764. 

  764. #define PERIOD_CNT		0x0008	/* Period Count							*/
    765. 

  765. #define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
    766. 

  766. #define TIN_SEL			0x0020	/* Timer Input Select					*/
    767. 

  767. #define OUT_DIS			0x0040	/* Output Pad Disable					*/
    768. 

  768. #define CLK_SEL			0x0080	/* Timer Clock Select					*/
    769. 

  769. #define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
    770. 

  770. #define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
    771. 

  771. #define ERR_TYP			0xC000	/* Error Type							*/
    772. 

  772. 

  773. /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
    774. 

  774. /* EBIU_AMGCTL Masks																	*/
    775. 

  775. #define AMCKEN			0x0001		/* Enable CLKOUT									*/
    776. 

  776. #define	AMBEN_NONE		0x0000		/* All Banks Disabled								*/
    777. 

  777. #define AMBEN_B0		0x0002		/* Enable Async Memory Bank 0 only					*/
    778. 

  778. #define AMBEN_B0_B1		0x0004		/* Enable Async Memory Banks 0 & 1 only				*/
    779. 

  779. #define AMBEN_B0_B1_B2	0x0006		/* Enable Async Memory Banks 0, 1, and 2			*/
    780. 

  780. #define AMBEN_ALL		0x0008		/* Enable Async Memory Banks (all) 0, 1, 2, and 3	*/
    781. 

  781. 

  782. /* EBIU_AMBCTL0 Masks																	*/
    783. 

  783. #define B0RDYEN			0x00000001  /* Bank 0 (B0) RDY Enable							*/
    784. 

  784. #define B0RDYPOL		0x00000002  /* B0 RDY Active High								*/
    785. 

  785. #define B0TT_1			0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle		*/
    786. 

  786. #define B0TT_2			0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles	*/
    787. 

  787. #define B0TT_3			0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles	*/
    788. 

  788. #define B0TT_4			0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles	*/
    789. 

  789. #define B0ST_1			0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle		*/
    790. 

  790. #define B0ST_2			0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles		*/
    791. 

  791. #define B0ST_3			0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles		*/
    792. 

  792. #define B0ST_4			0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles		*/
    793. 

  793. #define B0HT_1			0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
    794. 

  794. #define B0HT_2			0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
    795. 

  795. #define B0HT_3			0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
    796. 

  796. #define B0HT_0			0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
    797. 

  797. #define B0RAT_1			0x00000100  /* B0 Read Access Time = 1 cycle					*/
    798. 

  798. #define B0RAT_2			0x00000200  /* B0 Read Access Time = 2 cycles					*/
    799. 

  799. #define B0RAT_3			0x00000300  /* B0 Read Access Time = 3 cycles					*/
    800. 

  800. #define B0RAT_4			0x00000400  /* B0 Read Access Time = 4 cycles					*/
    801. 

  801. #define B0RAT_5			0x00000500  /* B0 Read Access Time = 5 cycles					*/
    802. 

  802. #define B0RAT_6			0x00000600  /* B0 Read Access Time = 6 cycles					*/
    803. 

  803. #define B0RAT_7			0x00000700  /* B0 Read Access Time = 7 cycles					*/
    804. 

  804. #define B0RAT_8			0x00000800  /* B0 Read Access Time = 8 cycles					*/
    805. 

  805. #define B0RAT_9			0x00000900  /* B0 Read Access Time = 9 cycles					*/
    806. 

  806. #define B0RAT_10		0x00000A00  /* B0 Read Access Time = 10 cycles					*/
    807. 

  807. #define B0RAT_11		0x00000B00  /* B0 Read Access Time = 11 cycles					*/
    808. 

  808. #define B0RAT_12		0x00000C00  /* B0 Read Access Time = 12 cycles					*/
    809. 

  809. #define B0RAT_13		0x00000D00  /* B0 Read Access Time = 13 cycles					*/
    810. 

  810. #define B0RAT_14		0x00000E00  /* B0 Read Access Time = 14 cycles					*/
    811. 

  811. #define B0RAT_15		0x00000F00  /* B0 Read Access Time = 15 cycles					*/
    812. 

  812. #define B0WAT_1			0x00001000  /* B0 Write Access Time = 1 cycle					*/
    813. 

  813. #define B0WAT_2			0x00002000  /* B0 Write Access Time = 2 cycles					*/
    814. 

  814. #define B0WAT_3			0x00003000  /* B0 Write Access Time = 3 cycles					*/
    815. 

  815. #define B0WAT_4			0x00004000  /* B0 Write Access Time = 4 cycles					*/
    816. 

  816. #define B0WAT_5			0x00005000  /* B0 Write Access Time = 5 cycles					*/
    817. 

  817. #define B0WAT_6			0x00006000  /* B0 Write Access Time = 6 cycles					*/
    818.