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- /*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF537_H
- #define _DEF_BF537_H
- /* Include all MMR and bit defines common to BF534 */
- #include "defBF534.h"
- /************************************************************************************
- ** Define EMAC Section Unique to BF536/BF537
- *************************************************************************************/
- /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
- #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
- #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
- #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
- #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
- #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
- #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
- #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
- #define EMAC_FLC 0xFFC0301C /* Flow Control Register */
- #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
- #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
- #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
- #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
- #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
- #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
- #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
- #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
- #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
- #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
- #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
- #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
- #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
- #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
- #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
- #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
- #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
- #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
- #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
- #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
- #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
- #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
- #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
- #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
- #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
- #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
- #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
- #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
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