levelDataPreprocessingThread.h 40 KB

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  1. /*
  2. * Copyright 2008-2010 Analog Devices Inc.
  3. *
  4. * Licensed under the Clear BSD license or the GPL-2 (or later)
  5. */
  6. #ifndef _DEF_BF538_H
  7. #define _DEF_BF538_H
  8. /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
  9. #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
  10. #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
  11. #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
  12. #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
  13. #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
  14. #define CHIPID 0xFFC00014 /* Chip ID Register */
  15. /* CHIPID Masks */
  16. #define CHIPID_VERSION 0xF0000000
  17. #define CHIPID_FAMILY 0x0FFFF000
  18. #define CHIPID_MANUFACTURE 0x00000FFE
  19. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
  20. #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
  21. #define SYSCR 0xFFC00104 /* System Configuration registe */
  22. #define SIC_RVECT 0xFFC00108
  23. #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
  24. #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
  25. #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
  26. #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
  27. #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
  28. #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
  29. #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
  30. #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
  31. #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
  32. #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
  33. #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
  34. #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
  35. #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
  36. /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
  37. #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
  38. #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
  39. #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
  40. /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
  41. #define RTC_STAT 0xFFC00300 /* RTC Status Register */
  42. #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
  43. #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
  44. #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
  45. #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
  46. #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
  47. #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
  48. /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
  49. #define UART0_THR 0xFFC00400 /* Transmit Holding register */
  50. #define UART0_RBR 0xFFC00400 /* Receive Buffer register */
  51. #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
  52. #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
  53. #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
  54. #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
  55. #define UART0_LCR 0xFFC0040C /* Line Control Register */
  56. #define UART0_MCR 0xFFC00410 /* Modem Control Register */
  57. #define UART0_LSR 0xFFC00414 /* Line Status Register */
  58. #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
  59. #define UART0_GCTL 0xFFC00424 /* Global Control Register */
  60. /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
  61. #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
  62. #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
  63. #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
  64. #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
  65. #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
  66. #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
  67. #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
  68. #define SPI0_REGBASE SPI0_CTL
  69. /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
  70. #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
  71. #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
  72. #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
  73. #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
  74. #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
  75. #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
  76. #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
  77. #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
  78. #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
  79. #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
  80. #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
  81. #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
  82. #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
  83. #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
  84. #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
  85. /* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
  86. #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
  87. #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
  88. #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
  89. #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
  90. #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
  91. #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
  92. #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
  93. #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
  94. #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
  95. #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
  96. #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
  97. #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
  98. #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
  99. #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
  100. #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
  101. #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
  102. #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
  103. /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
  104. #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
  105. #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
  106. #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
  107. #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
  108. #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
  109. #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
  110. #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
  111. #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
  112. #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
  113. #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
  114. #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
  115. #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
  116. #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
  117. #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
  118. #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
  119. #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
  120. #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
  121. #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
  122. #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
  123. #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
  124. #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
  125. #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
  126. /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
  127. #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
  128. #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
  129. #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
  130. #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
  131. #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
  132. #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
  133. #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
  134. #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
  135. #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
  136. #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
  137. #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
  138. #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
  139. #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
  140. #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
  141. #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
  142. #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
  143. #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
  144. #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
  145. #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
  146. #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
  147. #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
  148. #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
  149. /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
  150. /* Asynchronous Memory Controller */
  151. #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
  152. #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
  153. #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
  154. /* SDRAM Controller */
  155. #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
  156. #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
  157. #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
  158. #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
  159. /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
  160. #define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
  161. #define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
  162. /* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
  163. #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
  164. #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
  165. #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
  166. #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
  167. #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
  168. #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
  169. #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
  170. #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
  171. #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
  172. #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
  173. #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
  174. #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
  175. #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
  176. #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
  177. #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
  178. #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
  179. #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
  180. #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
  181. #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
  182. #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
  183. #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
  184. #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
  185. #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
  186. #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
  187. #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
  188. #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
  189. #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
  190. #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
  191. #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
  192. #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
  193. #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
  194. #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
  195. #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
  196. #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
  197. #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
  198. #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
  199. #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
  200. #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
  201. #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
  202. #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
  203. #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
  204. #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
  205. #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
  206. #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
  207. #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
  208. #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
  209. #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
  210. #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
  211. #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
  212. #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
  213. #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
  214. #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
  215. #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
  216. #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
  217. #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
  218. #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
  219. #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
  220. #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
  221. #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
  222. #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
  223. #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
  224. #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
  225. #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
  226. #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
  227. #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
  228. #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
  229. #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
  230. #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
  231. #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
  232. #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
  233. #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
  234. #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
  235. #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
  236. #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
  237. #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
  238. #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
  239. #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
  240. #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
  241. #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
  242. #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
  243. #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
  244. #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
  245. #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
  246. #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
  247. #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
  248. #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
  249. #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
  250. #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
  251. #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
  252. #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
  253. #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
  254. #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
  255. #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
  256. #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
  257. #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
  258. #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
  259. #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
  260. #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
  261. #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
  262. #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
  263. #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
  264. #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
  265. #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
  266. #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
  267. #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
  268. #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
  269. #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
  270. #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
  271. #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
  272. #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
  273. #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
  274. #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
  275. #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
  276. #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
  277. #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
  278. #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
  279. #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
  280. #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
  281. #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
  282. #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
  283. #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
  284. #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
  285. #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
  286. #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
  287. #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
  288. #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
  289. #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
  290. #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
  291. #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
  292. #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
  293. #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
  294. #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
  295. #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
  296. #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
  297. #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
  298. #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
  299. #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
  300. #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
  301. #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
  302. #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
  303. #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
  304. #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
  305. #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
  306. #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
  307. #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
  308. #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
  309. #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
  310. #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
  311. #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
  312. #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
  313. #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
  314. #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
  315. #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
  316. #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
  317. #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
  318. #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
  319. /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
  320. #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
  321. #define PPI_STATUS 0xFFC01004 /* PPI Status Register */
  322. #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
  323. #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
  324. #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
  325. /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
  326. #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
  327. #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
  328. #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
  329. #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
  330. #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
  331. #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
  332. #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
  333. #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
  334. #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
  335. #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
  336. #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
  337. #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
  338. #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
  339. #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
  340. #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
  341. #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
  342. #define TWI0_REGBASE TWI0_CLKDIV
  343. /* the following are for backwards compatibility */
  344. #define TWI0_PRESCALE TWI0_CONTROL
  345. #define TWI0_INT_SRC TWI0_INT_STAT
  346. #define TWI0_INT_ENABLE TWI0_INT_MASK
  347. /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
  348. /* GPIO Port C Register Names */
  349. #define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
  350. #define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
  351. #define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
  352. #define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
  353. #define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
  354. #define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
  355. #define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
  356. /* GPIO Port D Register Names */
  357. #define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
  358. #define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
  359. #define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
  360. #define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
  361. #define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
  362. #define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
  363. #define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
  364. /* GPIO Port E Register Names */
  365. #define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
  366. #define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
  367. #define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
  368. #define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
  369. #define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
  370. #define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
  371. #define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
  372. /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
  373. #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
  374. #define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
  375. /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
  376. #define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
  377. #define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
  378. #define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
  379. #define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
  380. #define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
  381. #define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
  382. #define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
  383. #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
  384. #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
  385. #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
  386. #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
  387. #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
  388. #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
  389. #define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
  390. #define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
  391. #define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
  392. #define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
  393. #define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
  394. #define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
  395. #define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
  396. #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
  397. #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
  398. #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
  399. #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
  400. #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
  401. #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
  402. #define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
  403. #define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
  404. #define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
  405. #define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
  406. #define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
  407. #define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
  408. #define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
  409. #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
  410. #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
  411. #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
  412. #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
  413. #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
  414. #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
  415. #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
  416. #define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
  417. #define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
  418. #define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
  419. #define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
  420. #define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
  421. #define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
  422. #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
  423. #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
  424. #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
  425. #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
  426. #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
  427. #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
  428. #define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
  429. #define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
  430. #define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
  431. #define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
  432. #define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
  433. #define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
  434. #define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
  435. #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
  436. #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
  437. #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
  438. #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
  439. #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
  440. #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
  441. #define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
  442. #define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
  443. #define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
  444. #define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
  445. #define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
  446. #define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
  447. #define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
  448. #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
  449. #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
  450. #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
  451. #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
  452. #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
  453. #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
  454. #define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
  455. #define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
  456. #define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
  457. #define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
  458. #define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
  459. #define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
  460. #define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
  461. #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
  462. #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
  463. #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
  464. #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
  465. #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
  466. #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
  467. #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
  468. #define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
  469. #define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
  470. #define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
  471. #define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
  472. #define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
  473. #define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
  474. #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
  475. #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
  476. #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
  477. #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
  478. #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
  479. #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
  480. #define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
  481. #define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
  482. #define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
  483. #define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
  484. #define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
  485. #define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
  486. #define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
  487. #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
  488. #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
  489. #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
  490. #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
  491. #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
  492. #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
  493. #define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
  494. #define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
  495. #define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
  496. #define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
  497. #define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
  498. #define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
  499. #define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
  500. #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
  501. #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
  502. #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
  503. #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
  504. #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
  505. #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
  506. #define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
  507. #define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
  508. #define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
  509. #define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
  510. #define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
  511. #define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
  512. #define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
  513. #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
  514. #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
  515. #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
  516. #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
  517. #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
  518. #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
  519. #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
  520. #define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
  521. #define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
  522. #define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
  523. #define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
  524. #define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
  525. #define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
  526. #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
  527. #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
  528. #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
  529. #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
  530. #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
  531. #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
  532. #define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
  533. #define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
  534. #define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
  535. #define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
  536. #define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */