aiot/waterDataDiscreteRateMining/averageCalculation/averageLiquidLevel.h

/*
 *	6522 Versatile Interface Adapter (VIA)
 *
 *	There are two of these on the Mac II. Some IRQ's are vectored
 *	via them as are assorted bits and bobs - eg rtc, adb. The picture
 *	is a bit incomplete as the Mac documentation doesn't cover this well
 */

#ifndef _ASM_MAC_VIA_H_
#define _ASM_MAC_VIA_H_

/*
 * Base addresses for the VIAs. There are two in every machine,
 * although on some machines the second is an RBV or an OSS.
 * The OSS is different enough that it's handled separately.
 *
 * Do not use these values directly; use the via1 and via2 variables
 * instead (and don't forget to check rbv_present when using via2!)
 */

#define VIA1_BASE	(0x50F00000)
#define VIA2_BASE	(0x50F02000)
#define  RBV_BASE	(0x50F26000)

/*
 *	Not all of these are true post MacII I think.
 *      CSA: probably the ones CHRP marks as 'unused' change purposes
 *      when the IWM becomes the SWIM.
 *      http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
 *      ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
 *
 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the
 * following changes for IIfx:
 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
 * Also, "All of the functionality of VIA2 has been moved to other chips".
 */

#define VIA1A_vSccWrReq	0x80	/* SCC write. (input)
				 * [CHRP] SCC WREQ: Reflects the state of the
				 * Wait/Request pins from the SCC.
				 * [Macintosh Family Hardware]
				 * as CHRP on SE/30,II,IIx,IIcx,IIci.
				 * on IIfx, "0 means an active request"
				 */
#define VIA1A_vRev8	0x40	/* Revision 8 board ???
                                 * [CHRP] En WaitReqB: Lets the WaitReq_L
				 * signal from port B of the SCC appear on
				 * the PA7 input pin. Output.
				 * [Macintosh Family] On the SE/30, this
				 * is the bit to flip screen buffers.
				 * 0=alternate, 1=main.
				 * on II,IIx,IIcx,IIci,IIfx this is a bit
				 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
				 */
#define VIA1A_vHeadSel	0x20	/* Head select for IWM.
				 * [CHRP] unused.
				 * [Macintosh Family] "Floppy disk
				 * state-control line SEL" on all but IIfx
				 */
#define VIA1A_vOverlay	0x10    /* [Macintosh Family] On SE/30,II,IIx,IIcx
				 * this bit enables the "Overlay" address
				 * map in the address decoders as it is on
				 * reset for mapping the ROM over the reset
				 * vector. 1=use overlay map.
				 * On the IIci,IIfx it is another bit of the
				 * CPU ID: 0=normal IIci, 1=IIci with parity
				 * feature or IIfx.
				 * [CHRP] En WaitReqA: Lets the WaitReq_L
				 * signal from port A of the SCC appear
				 * on the PA7 input pin (CHRP). Output.
				 * [MkLinux] "Drive Select"
				 *  (with 0x20 being 'disk head select')