temperatureMemoryDefinition.h 5.7 KB

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  1. #ifndef __ALPHA_LCA__H__
  2. #define __ALPHA_LCA__H__
  3. #include <asm/compiler.h>
  4. #include <asm/mce.h>
  5. /*
  6. * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,
  7. * for example).
  8. *
  9. * This file is based on:
  10. *
  11. * DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors
  12. * Hardware Reference Manual; Digital Equipment Corp.; May 1994;
  13. * Maynard, MA; Order Number: EC-N2681-71.
  14. */
  15. /*
  16. * NOTE: The LCA uses a Host Address Extension (HAE) register to access
  17. * PCI addresses that are beyond the first 27 bits of address
  18. * space. Updating the HAE requires an external cycle (and
  19. * a memory barrier), which tends to be slow. Instead of updating
  20. * it on each sparse memory access, we keep the current HAE value
  21. * cached in variable cache_hae. Only if the cached HAE differs
  22. * from the desired HAE value do we actually updated HAE register.
  23. * The HAE register is preserved by the interrupt handler entry/exit
  24. * code, so this scheme works even in the presence of interrupts.
  25. *
  26. * Dense memory space doesn't require the HAE, but is restricted to
  27. * aligned 32 and 64 bit accesses. Special Cycle and Interrupt
  28. * Acknowledge cycles may also require the use of the HAE. The LCA
  29. * limits I/O address space to the bottom 24 bits of address space,
  30. * but this easily covers the 16 bit ISA I/O address space.
  31. */
  32. /*
  33. * NOTE 2! The memory operations do not set any memory barriers, as
  34. * it's not needed for cases like a frame buffer that is essentially
  35. * memory-like. You need to do them by hand if the operations depend
  36. * on ordering.
  37. *
  38. * Similarly, the port I/O operations do a "mb" only after a write
  39. * operation: if an mb is needed before (as in the case of doing
  40. * memory mapped I/O first, and then a port I/O operation to the same
  41. * device), it needs to be done by hand.
  42. *
  43. * After the above has bitten me 100 times, I'll give up and just do
  44. * the mb all the time, but right now I'm hoping this will work out.
  45. * Avoiding mb's may potentially be a noticeable speed improvement,
  46. * but I can't honestly say I've tested it.
  47. *
  48. * Handling interrupts that need to do mb's to synchronize to
  49. * non-interrupts is another fun race area. Don't do it (because if
  50. * you do, I'll have to do *everything* with interrupts disabled,
  51. * ugh).
  52. */
  53. /*
  54. * Memory Controller registers:
  55. */
  56. #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
  57. #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
  58. #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
  59. #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
  60. #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
  61. #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
  62. #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
  63. #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
  64. #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
  65. #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
  66. #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
  67. #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
  68. #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
  69. #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
  70. #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
  71. #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
  72. #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
  73. #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
  74. #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
  75. /*
  76. * I/O Controller registers:
  77. */
  78. #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
  79. #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
  80. #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
  81. #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
  82. #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
  83. #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
  84. #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
  85. #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
  86. #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
  87. #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
  88. #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
  89. #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
  90. #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
  91. #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
  92. #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
  93. #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
  94. #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
  95. #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
  96. #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
  97. #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
  98. #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
  99. #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
  100. /*
  101. * Memory spaces:
  102. */
  103. #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
  104. #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
  105. #define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
  106. #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
  107. #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
  108. /*
  109. * Bit definitions for I/O Controller status register 0:
  110. */
  111. #define LCA_IOC_STAT0_CMD 0xf
  112. #define LCA_IOC_STAT0_ERR (1<<4)
  113. #define LCA_IOC_STAT0_LOST (1<<5)
  114. #define LCA_IOC_STAT0_THIT (1<<6)
  115. #define LCA_IOC_STAT0_TREF (1<<7)
  116. #define LCA_IOC_STAT0_CODE_SHIFT 8
  117. #define LCA_IOC_STAT0_CODE_MASK 0x7
  118. #define LCA_IOC_STAT0_P_NBR_SHIFT 13
  119. #define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
  120. #define LCA_HAE_ADDRESS LCA_IOC_HAE
  121. /* LCA PMR Power Management register defines */
  122. #define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL)
  123. #define LCA_PMR_PDIV 0x7 /* Primary clock divisor */
  124. #define LCA_PMR_ODIV 0x38 /* Override clock divisor */
  125. #define LCA_PMR_INTO 0x40 /* Interrupt override */
  126. #define LCA_PMR_DMAO 0x80 /* DMA override */
  127. #define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */
  128. #define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */
  129. #define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L