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aiot
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efDataDiscreteRateMining
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dataSharedMemory
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memoryOperation.h

memoryOperation.h 10 KB
文件歷史 原始文件

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  1. /*
    2. 

  2.  * OMAP44xx CM2 instance offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009-2011 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2009-2010 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Paul Walmsley (paul@pwsan.com)
    8. 

  8.  * Rajendra Nayak (rnayak@ti.com)
    9. 

  9.  * Benoit Cousson (b-cousson@ti.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  *
    21. 

  21.  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
    22. 

  22.  *     or "OMAP4430".
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
    26. 

  26. #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
    27. 

  27. 

  28. /* CM2 base address */
    29. 

  29. #define OMAP4430_CM2_BASE		0x4a008000
    30. 

  30. 

  31. #define OMAP44XX_CM2_REGADDR(inst, reg)				\
    32. 

  32. 	OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
    33. 

  33. 

  34. /* CM2 instances */
    35. 

  35. #define OMAP4430_CM2_OCP_SOCKET_INST	0x0000
    36. 

  36. #define OMAP4430_CM2_CKGEN_INST		0x0100
    37. 

  37. #define OMAP4430_CM2_ALWAYS_ON_INST	0x0600
    38. 

  38. #define OMAP4430_CM2_CORE_INST		0x0700
    39. 

  39. #define OMAP4430_CM2_IVAHD_INST		0x0f00
    40. 

  40. #define OMAP4430_CM2_CAM_INST		0x1000
    41. 

  41. #define OMAP4430_CM2_DSS_INST		0x1100
    42. 

  42. #define OMAP4430_CM2_GFX_INST		0x1200
    43. 

  43. #define OMAP4430_CM2_L3INIT_INST	0x1300
    44. 

  44. #define OMAP4430_CM2_L4PER_INST		0x1400
    45. 

  45. #define OMAP4430_CM2_CEFUSE_INST	0x1600
    46. 

  46. #define OMAP4430_CM2_RESTORE_INST	0x1e00
    47. 

  47. #define OMAP4430_CM2_INSTR_INST		0x1f00
    48. 

  48. 

  49. /* CM2 clockdomain register offsets (from instance start) */
    50. 

  50. #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS	0x0000
    51. 

  51. #define OMAP4430_CM2_CORE_L3_1_CDOFFS		0x0000
    52. 

  52. #define OMAP4430_CM2_CORE_L3_2_CDOFFS		0x0100
    53. 

  53. #define OMAP4430_CM2_CORE_DUCATI_CDOFFS		0x0200
    54. 

  54. #define OMAP4430_CM2_CORE_SDMA_CDOFFS		0x0300
    55. 

  55. #define OMAP4430_CM2_CORE_MEMIF_CDOFFS		0x0400
    56. 

  56. #define OMAP4430_CM2_CORE_D2D_CDOFFS		0x0500
    57. 

  57. #define OMAP4430_CM2_CORE_L4CFG_CDOFFS		0x0600
    58. 

  58. #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS	0x0700
    59. 

  59. #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS		0x0000
    60. 

  60. #define OMAP4430_CM2_CAM_CAM_CDOFFS		0x0000
    61. 

  61. #define OMAP4430_CM2_DSS_DSS_CDOFFS		0x0000
    62. 

  62. #define OMAP4430_CM2_GFX_GFX_CDOFFS		0x0000
    63. 

  63. #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS	0x0000
    64. 

  64. #define OMAP4430_CM2_L4PER_L4PER_CDOFFS		0x0000
    65. 

  65. #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS		0x0180
    66. 

  66. #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS	0x0000
    67. 

  67. 

  68. /* CM2 */
    69. 

  69. 

  70. /* CM2.OCP_SOCKET_CM2 register offsets */
    71. 

  71. #define OMAP4_REVISION_CM2_OFFSET			0x0000
    72. 

  72. #define OMAP4430_REVISION_CM2				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
    73. 

  73. #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET		0x0040
    74. 

  74. #define OMAP4430_CM_CM2_PROFILING_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
    75. 

  75. 

  76. /* CM2.CKGEN_CM2 register offsets */
    77. 

  77. #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET		0x0000
    78. 

  78. #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
    79. 

  79. #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET		0x0004
    80. 

  80. #define OMAP4430_CM_CLKSEL_USB_60MHZ			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
    81. 

  81. #define OMAP4_CM_SCALE_FCLK_OFFSET			0x0008
    82. 

  82. #define OMAP4430_CM_SCALE_FCLK				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
    83. 

  83. #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET			0x0010
    84. 

  84. #define OMAP4430_CM_CORE_DVFS_PERF1			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
    85. 

  85. #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET			0x0014
    86. 

  86. #define OMAP4430_CM_CORE_DVFS_PERF2			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
    87. 

  87. #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET			0x0018
    88. 

  88. #define OMAP4430_CM_CORE_DVFS_PERF3			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
    89. 

  89. #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET			0x001c
    90. 

  90. #define OMAP4430_CM_CORE_DVFS_PERF4			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
    91. 

  91. #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET		0x0024
    92. 

  92. #define OMAP4430_CM_CORE_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
    93. 

  93. #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET		0x0028
    94. 

  94. #define OMAP4430_CM_IVA_DVFS_PERF_TESLA			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
    95. 

  95. #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET		0x002c
    96. 

  96. #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
    97. 

  97. #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET		0x0030
    98. 

  98. #define OMAP4430_CM_IVA_DVFS_PERF_ABE			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
    99. 

  99. #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET		0x0038
    100. 

  100. #define OMAP4430_CM_IVA_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
    101. 

  101. #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET		0x0040
    102. 

  102. #define OMAP4430_CM_CLKMODE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
    103. 

  103. #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET			0x0044
    104. 

  104. #define OMAP4430_CM_IDLEST_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
    105. 

  105. #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET		0x0048
    106. 

  106. #define OMAP4430_CM_AUTOIDLE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
    107. 

  107. #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET			0x004c
    108. 

  108. #define OMAP4430_CM_CLKSEL_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
    109. 

  109. #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET			0x0050
    110. 

  110. #define OMAP4430_CM_DIV_M2_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
    111. 

  111. #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET			0x0054
    112. 

  112. #define OMAP4430_CM_DIV_M3_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
    113. 

  113. #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET			0x0058
    114. 

  114. #define OMAP4430_CM_DIV_M4_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
    115. 

  115. #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET			0x005c
    116. 

  116. #define OMAP4430_CM_DIV_M5_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
    117. 

  117. #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET			0x0060
    118. 

  118. #define OMAP4430_CM_DIV_M6_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
    119. 

  119. #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET			0x0064
    120. 

  120. #define OMAP4430_CM_DIV_M7_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
    121. 

  121. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
    122. 

  122. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
    123. 

  123. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
    124. 

  124. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
    125. 

  125. #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080
    126. 

  126. #define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
    127. 

  127. #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
    128. 

  128. #define OMAP4430_CM_IDLEST_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
    129. 

  129. #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET		0x0088
    130. 

  130. #define OMAP4430_CM_AUTOIDLE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
    131. 

  131. #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET			0x008c
    132. 

  132. #define OMAP4430_CM_CLKSEL_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
    133. 

  133. #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
    134. 

  134. #define OMAP4430_CM_DIV_M2_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
    135. 

  135. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
    136. 

  136. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
    137. 

  137. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
    138. 

  138. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
    139. 

  139. #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET		0x00b4
    140. 

  140. #define OMAP4430_CM_CLKDCOLDO_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
    141. 

  141. #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET		0x00c0
    142. 

  142. #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
    143. 

  143. #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET		0x00c4
    144. 

  144. #define OMAP4430_CM_IDLEST_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
    145. 

  145. #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET		0x00c8
    146. 

  146. #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
    147. 

  147. #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET		0x00cc
    148. 

  148. #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
    149. 

  149. #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET		0x00d0
    150. 

  150. #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
    151. 

  151. #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET	0x00e8
    152. 

  152. #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
    153. 

  153. #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec
    154. 

  154. #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
    155. 

  155. 

  156. /* CM2.ALWAYS_ON_CM2 register offsets */
    157. 

  157. #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET			0x0000
    158. 

  158. #define OMAP4430_CM_ALWON_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
    159. 

  159. #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET		0x0020
    160. 

  160. #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
    161. 

  161. #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET		0x0028
    162. 

  162. #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
    163. 

  163. #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET		0x0030
    164. 

  164. #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
    165. 

  165. #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET		0x0038
    166. 

  166. #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
    167. 

  167. #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET		0x0040
    168. 

  168. #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
    169. 

  169. 

  170. /* CM2.CORE_CM2 register offsets */
    171. 

  171. #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET			0x0000
    172. 

  172. #define OMAP4430_CM_L3_1_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
    173. 

  173. #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET			0x0008
    174. 

  174. #define OMAP4430_CM_L3_1_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
    175. 

  175. #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET		0x0020
    176. 

  176. #define OMAP4430_CM_L3_1_L3_1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
    177. 

  177. #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET			0x0100
    178. 

  178. #define OMAP4430_CM_L3_2_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
    179. 

  179. #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET			0x0108
    180. 

  180. #define OMAP4430_CM_L3_2_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
    181. 

  181. #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET		0x0120
    182. 

  182. #define OMAP4430_CM_L3_2_L3_2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
    183. 

  183. #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET		0x0128
    184.