aiot/efDataDiscreteRateMining/monitoringDataProcessing/preliminaryDataProcessing.h

/*
 * SA-1101.h
 *
 * Copyright (c) Peter Danielsson 1999
 *
 * Definition of constants related to the sa1101
 * support chip for the sa1100
 *
 */


/* Be sure that virtual mapping is defined right */
#ifndef __ASM_ARCH_HARDWARE_H
#error You must include hardware.h not SA-1101.h
#endif

#ifndef SA1101_BASE
#error You must define SA-1101 physical base address
#endif

#ifndef LANGUAGE
# ifdef __ASSEMBLY__
#  define LANGUAGE Assembly
# else
#  define LANGUAGE C
# endif
#endif

/*
 * We have mapped the sa1101 depending on the value of SA1101_BASE.
 * It then appears from 0xf4000000.
 */

#define SA1101_p2v( x )         ((x) - SA1101_BASE + 0xf4000000)
#define SA1101_v2p( x )         ((x) - 0xf4000000  + SA1101_BASE)

#ifndef SA1101_p2v
#define SA1101_p2v(PhAdd)  (PhAdd)
#endif

#include <mach/bitfield.h>

#define C               0
#define Assembly        1


/*
 * Memory map
 */

#define __SHMEM_CONTROL0	0x00000000
#define __SYSTEM_CONTROL1	0x00000400
#define __ARBITER		0x00020000
#define __SYSTEM_CONTROL2	0x00040000
#define __SYSTEM_CONTROL3	0x00060000
#define __PARALLEL_PORT		0x00080000
#define __VIDMEM_CONTROL	0x00100000
#define __UPDATE_FIFO		0x00120000
#define __SHMEM_CONTROL1	0x00140000
#define __INTERRUPT_CONTROL	0x00160000
#define __USB_CONTROL		0x00180000
#define __TRACK_INTERFACE	0x001a0000
#define __MOUSE_INTERFACE	0x001b0000
#define __KEYPAD_INTERFACE	0x001c0000
#define __PCMCIA_INTERFACE	0x001e0000
#define	__VGA_CONTROL		0x00200000
#define __GPIO_INTERFACE	0x00300000

/*
 * Macro that calculates real address for registers in the SA-1101
 */

#define _SA1101( x )    ((x) + SA1101_BASE)

/*
 * Interface and shared memory controller registers
 *
 * Registers
 *	SKCR		SA-1101 control register (read/write)
 *	SMCR		Shared Memory Controller Register
 *	SNPR		Snoop Register
 */

#define _SKCR		_SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
#define _SMCR		_SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
#define _SNPR		_SA1101( 0x00140400 ) /* Snoop Reg. */

#if LANGUAGE == C
#define SKCR		(*((volatile Word *) SA1101_p2v (_SKCR)))
#define SMCR		(*((volatile Word *) SA1101_p2v (_SMCR)))
#define SNPR		(*((volatile Word *) SA1101_p2v (_SNPR)))

#define SKCR_PLLEn	  0x0001	  /* Enable On-Chip PLL */
#define SKCR_BCLKEn	  0x0002	  /* Enables BCLK */
#define SKCR_Sleep	  0x0004	  /* Sleep Mode */
#define SKCR_IRefEn	  0x0008	  /* DAC Iref input enable */
#define SKCR_VCOON	  0x0010	  /* VCO bias */
#define SKCR_ScanTestEn	  0x0020	  /* Enables scan test */
#define SKCR_ClockTestEn  0x0040	  /* Enables clock test */

#define SMCR_DCAC	  Fld(2,0)	  /* Number of column address bits */
#define SMCR_DRAC	  Fld(2,2)	  /* Number of row address bits */
#define SMCR_ArbiterBias  0x0008	  /* favor video or USB */
#define SMCR_TopVidMem	  Fld(4,5)	  /* Top 4 bits of vidmem addr. */

#define SMCR_ColAdrBits( x )		  /* col. addr bits 8..11 */ \
	(( (x) - 8 ) << FShft (SMCR_DCAC))
#define SMCR_RowAdrBits( x )		  /* row addr bits 9..12 */\
	(( (x) - 9 ) << FShft (SMCR_DRAC))

#define SNPR_VFBstart	  Fld(12,0)	/* Video frame buffer addr */
#define SNPR_VFBsize	  Fld(11,12)	/* Video frame buffer size */
#define SNPR_WholeBank	  (1 << 23)	/* Whole bank bit */
#define SNPR_BankSelect	  Fld(2,27)	/* Bank select */
#define SNPR_SnoopEn	  (1 << 31)	/* Enable snoop operation */

#define SNPR_Set_VFBsize( x )   /* set frame buffer size (in kb) */ \
	( (x) << FShft (SNPR_VFBsize))
#define SNPR_Select_Bank(x)     /* select bank 0 or 1 */  \
	(( (x) + 1 ) << FShft (SNPR_BankSelect ))

#endif /* LANGUAGE == C */

/*
 * Video Memory Controller
 *
 * Registers
 *    VMCCR	Configuration register
 *    VMCAR	VMC address register
 *    VMCDR	VMC data register
 *
 */