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aiot
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waterInvestigationHiddenDanger
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analysisOfLeakageHiddenDanger
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analysisOfLiquidLevelData.h

analysisOfLiquidLevelData.h 2.9 KB
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  1. #ifndef _OPSPUT_OPSPUT_PLD_H
    2. 

  2. #define _OPSPUT_OPSPUT_PLD_H
    3. 

  3. 

  4. /*
    5. 

  5.  * include/asm-m32r/opsput/opsput_pld.h
    6. 

  6.  *
    7. 

  7.  * Definitions for Programmable Logic Device(PLD) on OPSPUT board.
    8. 

  8.  *
    9. 

  9.  * Copyright (c) 2002	Takeo Takahashi
    10. 

  10.  *
    11. 

  11.  * This file is subject to the terms and conditions of the GNU General
    12. 

  12.  * Public License.  See the file "COPYING" in the main directory of
    13. 

  13.  * this archive for more details.
    14. 

  14.  */
    15. 

  15. 

  16. #define PLD_PLAT_BASE		0x1cc00000
    17. 

  17. 

  18. #ifndef __ASSEMBLY__
    19. 

  19. /*
    20. 

  20.  * C functions use non-cache address.
    21. 

  21.  */
    22. 

  22. #define PLD_BASE		(PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
    23. 

  23. #define __reg8			(volatile unsigned char *)
    24. 

  24. #define __reg16			(volatile unsigned short *)
    25. 

  25. #define __reg32			(volatile unsigned int *)
    26. 

  26. #else
    27. 

  27. #define PLD_BASE		(PLD_PLAT_BASE + NONCACHE_OFFSET)
    28. 

  28. #define __reg8
    29. 

  29. #define __reg16
    30. 

  30. #define __reg32
    31. 

  31. #endif /* __ASSEMBLY__ */
    32. 

  32. 

  33. /* CFC */
    34. 

  34. #define	PLD_CFRSTCR		__reg16(PLD_BASE + 0x0000)
    35. 

  35. #define PLD_CFSTS		__reg16(PLD_BASE + 0x0002)
    36. 

  36. #define PLD_CFIMASK		__reg16(PLD_BASE + 0x0004)
    37. 

  37. #define PLD_CFBUFCR		__reg16(PLD_BASE + 0x0006)
    38. 

  38. #define PLD_CFVENCR		__reg16(PLD_BASE + 0x0008)
    39. 

  39. #define PLD_CFCR0		__reg16(PLD_BASE + 0x000a)
    40. 

  40. #define PLD_CFCR1		__reg16(PLD_BASE + 0x000c)
    41. 

  41. #define PLD_IDERSTCR		__reg16(PLD_BASE + 0x0010)
    42. 

  42. 

  43. /* MMC */
    44. 

  44. #define PLD_MMCCR		__reg16(PLD_BASE + 0x4000)
    45. 

  45. #define PLD_MMCMOD		__reg16(PLD_BASE + 0x4002)
    46. 

  46. #define PLD_MMCSTS		__reg16(PLD_BASE + 0x4006)
    47. 

  47. #define PLD_MMCBAUR		__reg16(PLD_BASE + 0x400a)
    48. 

  48. #define PLD_MMCCMDBCUT		__reg16(PLD_BASE + 0x400c)
    49. 

  49. #define PLD_MMCCDTBCUT		__reg16(PLD_BASE + 0x400e)
    50. 

  50. #define PLD_MMCDET		__reg16(PLD_BASE + 0x4010)
    51. 

  51. #define PLD_MMCWP		__reg16(PLD_BASE + 0x4012)
    52. 

  52. #define PLD_MMCWDATA		__reg16(PLD_BASE + 0x5000)
    53. 

  53. #define PLD_MMCRDATA		__reg16(PLD_BASE + 0x6000)
    54. 

  54. #define PLD_MMCCMDDATA		__reg16(PLD_BASE + 0x7000)
    55. 

  55. #define PLD_MMCRSPDATA		__reg16(PLD_BASE + 0x7006)
    56. 

  56. 

  57. /* ICU
    58. 

  58.  *  ICUISTS:	status register
    59. 

  59.  *  ICUIREQ0: 	request register
    60. 

  60.  *  ICUIREQ1: 	request register
    61. 

  61.  *  ICUCR3:	control register for CFIREQ# interrupt
    62. 

  62.  *  ICUCR4:	control register for CFC Card insert interrupt
    63. 

  63.  *  ICUCR5:	control register for CFC Card eject interrupt
    64. 

  64.  *  ICUCR6:	control register for external interrupt
    65. 

  65.  *  ICUCR11:	control register for MMC Card insert/eject interrupt
    66. 

  66.  *  ICUCR13:	control register for SC error interrupt
    67. 

  67.  *  ICUCR14:	control register for SC receive interrupt
    68. 

  68.  *  ICUCR15:	control register for SC send interrupt
    69. 

  69.  *  ICUCR16:	control register for SIO0 receive interrupt
    70. 

  70.  *  ICUCR17:	control register for SIO0 send interrupt
    71. 

  71.  */
    72. 

  72. #if !defined(CONFIG_PLAT_USRV)
    73. 

  73. #define PLD_IRQ_INT0		(OPSPUT_PLD_IRQ_BASE + 0)	/* None */
    74. 

  74. #define PLD_IRQ_INT1		(OPSPUT_PLD_IRQ_BASE + 1)	/* reserved */
    75. 

  75. #define PLD_IRQ_INT2		(OPSPUT_PLD_IRQ_BASE + 2)	/* reserved */
    76. 

  76. #define PLD_IRQ_CFIREQ		(OPSPUT_PLD_IRQ_BASE + 3)	/* CF IREQ */
    77. 

  77. #define PLD_IRQ_CFC_INSERT	(OPSPUT_PLD_IRQ_BASE + 4)	/* CF Insert */
    78. 

  78. #define PLD_IRQ_CFC_EJECT	(OPSPUT_PLD_IRQ_BASE + 5)	/* CF Eject */
    79. 

  79. #define PLD_IRQ_EXINT		(OPSPUT_PLD_IRQ_BASE + 6)	/* EXINT */
    80. 

  80. #define PLD_IRQ_INT7		(OPSPUT_PLD_IRQ_BASE + 7)	/* reserved */
    81.