memoryOperation.c 37 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <media/s5p_hdmi.h>
  34. #include <asm/irq.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <linux/platform_data/ata-samsung_cf.h>
  46. #include <linux/platform_data/usb-ehci-s5p.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hdmi.h>
  50. #include <linux/platform_data/hwmon-s3c.h>
  51. #include <linux/platform_data/i2c-s3c2410.h>
  52. #include <plat/keypad.h>
  53. #include <linux/platform_data/mmc-s3cmci.h>
  54. #include <linux/platform_data/mtd-nand-s3c2410.h>
  55. #include <plat/sdhci.h>
  56. #include <linux/platform_data/touchscreen-s3c2410.h>
  57. #include <linux/platform_data/usb-s3c2410_udc.h>
  58. #include <linux/platform_data/usb-ohci-s3c2410.h>
  59. #include <plat/usb-phy.h>
  60. #include <plat/regs-iic.h>
  61. #include <plat/regs-serial.h>
  62. #include <plat/regs-spi.h>
  63. #include <linux/platform_data/spi-s3c64xx.h>
  64. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  65. /* AC97 */
  66. #ifdef CONFIG_CPU_S3C2440
  67. static struct resource s3c_ac97_resource[] = {
  68. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  69. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  70. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  71. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  72. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  73. };
  74. struct platform_device s3c_device_ac97 = {
  75. .name = "samsung-ac97",
  76. .id = -1,
  77. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  78. .resource = s3c_ac97_resource,
  79. .dev = {
  80. .dma_mask = &samsung_device_dma_mask,
  81. .coherent_dma_mask = DMA_BIT_MASK(32),
  82. }
  83. };
  84. #endif /* CONFIG_CPU_S3C2440 */
  85. /* ADC */
  86. #ifdef CONFIG_PLAT_S3C24XX
  87. static struct resource s3c_adc_resource[] = {
  88. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  89. [1] = DEFINE_RES_IRQ(IRQ_TC),
  90. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  91. };
  92. struct platform_device s3c_device_adc = {
  93. .name = "s3c24xx-adc",
  94. .id = -1,
  95. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  96. .resource = s3c_adc_resource,
  97. };
  98. #endif /* CONFIG_PLAT_S3C24XX */
  99. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  100. static struct resource s3c_adc_resource[] = {
  101. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  102. [1] = DEFINE_RES_IRQ(IRQ_TC),
  103. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  104. };
  105. struct platform_device s3c_device_adc = {
  106. .name = "samsung-adc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  109. .resource = s3c_adc_resource,
  110. };
  111. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  112. /* Camif Controller */
  113. #ifdef CONFIG_CPU_S3C2440
  114. static struct resource s3c_camif_resource[] = {
  115. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  116. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  117. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  118. };
  119. struct platform_device s3c_device_camif = {
  120. .name = "s3c2440-camif",
  121. .id = -1,
  122. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  123. .resource = s3c_camif_resource,
  124. .dev = {
  125. .dma_mask = &samsung_device_dma_mask,
  126. .coherent_dma_mask = DMA_BIT_MASK(32),
  127. }
  128. };
  129. #endif /* CONFIG_CPU_S3C2440 */
  130. /* ASOC DMA */
  131. struct platform_device samsung_asoc_idma = {
  132. .name = "samsung-idma",
  133. .id = -1,
  134. .dev = {
  135. .dma_mask = &samsung_device_dma_mask,
  136. .coherent_dma_mask = DMA_BIT_MASK(32),
  137. }
  138. };
  139. /* FB */
  140. #ifdef CONFIG_S3C_DEV_FB
  141. static struct resource s3c_fb_resource[] = {
  142. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  143. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  144. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  145. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  146. };
  147. struct platform_device s3c_device_fb = {
  148. .name = "s3c-fb",
  149. .id = -1,
  150. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  151. .resource = s3c_fb_resource,
  152. .dev = {
  153. .dma_mask = &samsung_device_dma_mask,
  154. .coherent_dma_mask = DMA_BIT_MASK(32),
  155. },
  156. };
  157. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  158. {
  159. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  160. &s3c_device_fb);
  161. }
  162. #endif /* CONFIG_S3C_DEV_FB */
  163. /* FIMC */
  164. #ifdef CONFIG_S5P_DEV_FIMC0
  165. static struct resource s5p_fimc0_resource[] = {
  166. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  167. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  168. };
  169. struct platform_device s5p_device_fimc0 = {
  170. .name = "s5p-fimc",
  171. .id = 0,
  172. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  173. .resource = s5p_fimc0_resource,
  174. .dev = {
  175. .dma_mask = &samsung_device_dma_mask,
  176. .coherent_dma_mask = DMA_BIT_MASK(32),
  177. },
  178. };
  179. struct platform_device s5p_device_fimc_md = {
  180. .name = "s5p-fimc-md",
  181. .id = -1,
  182. };
  183. #endif /* CONFIG_S5P_DEV_FIMC0 */
  184. #ifdef CONFIG_S5P_DEV_FIMC1
  185. static struct resource s5p_fimc1_resource[] = {
  186. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  187. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  188. };
  189. struct platform_device s5p_device_fimc1 = {
  190. .name = "s5p-fimc",
  191. .id = 1,
  192. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  193. .resource = s5p_fimc1_resource,
  194. .dev = {
  195. .dma_mask = &samsung_device_dma_mask,
  196. .coherent_dma_mask = DMA_BIT_MASK(32),
  197. },
  198. };
  199. #endif /* CONFIG_S5P_DEV_FIMC1 */
  200. #ifdef CONFIG_S5P_DEV_FIMC2
  201. static struct resource s5p_fimc2_resource[] = {
  202. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  203. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  204. };
  205. struct platform_device s5p_device_fimc2 = {
  206. .name = "s5p-fimc",
  207. .id = 2,
  208. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  209. .resource = s5p_fimc2_resource,
  210. .dev = {
  211. .dma_mask = &samsung_device_dma_mask,
  212. .coherent_dma_mask = DMA_BIT_MASK(32),
  213. },
  214. };
  215. #endif /* CONFIG_S5P_DEV_FIMC2 */
  216. #ifdef CONFIG_S5P_DEV_FIMC3
  217. static struct resource s5p_fimc3_resource[] = {
  218. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  219. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  220. };
  221. struct platform_device s5p_device_fimc3 = {
  222. .name = "s5p-fimc",
  223. .id = 3,
  224. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  225. .resource = s5p_fimc3_resource,
  226. .dev = {
  227. .dma_mask = &samsung_device_dma_mask,
  228. .coherent_dma_mask = DMA_BIT_MASK(32),
  229. },
  230. };
  231. #endif /* CONFIG_S5P_DEV_FIMC3 */
  232. /* G2D */
  233. #ifdef CONFIG_S5P_DEV_G2D
  234. static struct resource s5p_g2d_resource[] = {
  235. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  236. [1] = DEFINE_RES_IRQ(IRQ_2D),
  237. };
  238. struct platform_device s5p_device_g2d = {
  239. .name = "s5p-g2d",
  240. .id = 0,
  241. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  242. .resource = s5p_g2d_resource,
  243. .dev = {
  244. .dma_mask = &samsung_device_dma_mask,
  245. .coherent_dma_mask = DMA_BIT_MASK(32),
  246. },
  247. };
  248. #endif /* CONFIG_S5P_DEV_G2D */
  249. #ifdef CONFIG_S5P_DEV_JPEG
  250. static struct resource s5p_jpeg_resource[] = {
  251. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  252. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  253. };
  254. struct platform_device s5p_device_jpeg = {
  255. .name = "s5p-jpeg",
  256. .id = 0,
  257. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  258. .resource = s5p_jpeg_resource,
  259. .dev = {
  260. .dma_mask = &samsung_device_dma_mask,
  261. .coherent_dma_mask = DMA_BIT_MASK(32),
  262. },
  263. };
  264. #endif /* CONFIG_S5P_DEV_JPEG */
  265. /* FIMD0 */
  266. #ifdef CONFIG_S5P_DEV_FIMD0
  267. static struct resource s5p_fimd0_resource[] = {
  268. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  269. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  270. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  271. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  272. };
  273. struct platform_device s5p_device_fimd0 = {
  274. .name = "s5p-fb",
  275. .id = 0,
  276. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  277. .resource = s5p_fimd0_resource,
  278. .dev = {
  279. .dma_mask = &samsung_device_dma_mask,
  280. .coherent_dma_mask = DMA_BIT_MASK(32),
  281. },
  282. };
  283. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  284. {
  285. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  286. &s5p_device_fimd0);
  287. }
  288. #endif /* CONFIG_S5P_DEV_FIMD0 */
  289. /* HWMON */
  290. #ifdef CONFIG_S3C_DEV_HWMON
  291. struct platform_device s3c_device_hwmon = {
  292. .name = "s3c-hwmon",
  293. .id = -1,
  294. .dev.parent = &s3c_device_adc.dev,
  295. };
  296. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  297. {
  298. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  299. &s3c_device_hwmon);
  300. }
  301. #endif /* CONFIG_S3C_DEV_HWMON */
  302. /* HSMMC */
  303. #ifdef CONFIG_S3C_DEV_HSMMC
  304. static struct resource s3c_hsmmc_resource[] = {
  305. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  306. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  307. };
  308. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  309. .max_width = 4,
  310. .host_caps = (MMC_CAP_4_BIT_DATA |
  311. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  312. };
  313. struct platform_device s3c_device_hsmmc0 = {
  314. .name = "s3c-sdhci",
  315. .id = 0,
  316. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  317. .resource = s3c_hsmmc_resource,
  318. .dev = {
  319. .dma_mask = &samsung_device_dma_mask,
  320. .coherent_dma_mask = DMA_BIT_MASK(32),
  321. .platform_data = &s3c_hsmmc0_def_platdata,
  322. },
  323. };
  324. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  325. {
  326. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  327. }
  328. #endif /* CONFIG_S3C_DEV_HSMMC */
  329. #ifdef CONFIG_S3C_DEV_HSMMC1
  330. static struct resource s3c_hsmmc1_resource[] = {
  331. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  332. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  333. };
  334. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  335. .max_width = 4,
  336. .host_caps = (MMC_CAP_4_BIT_DATA |
  337. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  338. };
  339. struct platform_device s3c_device_hsmmc1 = {
  340. .name = "s3c-sdhci",
  341. .id = 1,
  342. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  343. .resource = s3c_hsmmc1_resource,
  344. .dev = {
  345. .dma_mask = &samsung_device_dma_mask,
  346. .coherent_dma_mask = DMA_BIT_MASK(32),
  347. .platform_data = &s3c_hsmmc1_def_platdata,
  348. },
  349. };
  350. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  351. {
  352. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  353. }
  354. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  355. /* HSMMC2 */
  356. #ifdef CONFIG_S3C_DEV_HSMMC2
  357. static struct resource s3c_hsmmc2_resource[] = {
  358. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  359. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  360. };
  361. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  362. .max_width = 4,
  363. .host_caps = (MMC_CAP_4_BIT_DATA |
  364. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  365. };
  366. struct platform_device s3c_device_hsmmc2 = {
  367. .name = "s3c-sdhci",
  368. .id = 2,
  369. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  370. .resource = s3c_hsmmc2_resource,
  371. .dev = {
  372. .dma_mask = &samsung_device_dma_mask,
  373. .coherent_dma_mask = DMA_BIT_MASK(32),
  374. .platform_data = &s3c_hsmmc2_def_platdata,
  375. },
  376. };
  377. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  378. {
  379. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  380. }
  381. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  382. #ifdef CONFIG_S3C_DEV_HSMMC3
  383. static struct resource s3c_hsmmc3_resource[] = {
  384. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  385. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  386. };
  387. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  388. .max_width = 4,
  389. .host_caps = (MMC_CAP_4_BIT_DATA |
  390. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  391. };
  392. struct platform_device s3c_device_hsmmc3 = {
  393. .name = "s3c-sdhci",
  394. .id = 3,
  395. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  396. .resource = s3c_hsmmc3_resource,
  397. .dev = {
  398. .dma_mask = &samsung_device_dma_mask,
  399. .coherent_dma_mask = DMA_BIT_MASK(32),
  400. .platform_data = &s3c_hsmmc3_def_platdata,
  401. },
  402. };
  403. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  404. {
  405. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  406. }
  407. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  408. /* I2C */
  409. static struct resource s3c_i2c0_resource[] = {
  410. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  411. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  412. };
  413. struct platform_device s3c_device_i2c0 = {
  414. .name = "s3c2410-i2c",
  415. .id = 0,
  416. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  417. .resource = s3c_i2c0_resource,
  418. };
  419. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  420. .flags = 0,
  421. .slave_addr = 0x10,
  422. .frequency = 100*1000,
  423. .sda_delay = 100,
  424. };
  425. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  426. {
  427. struct s3c2410_platform_i2c *npd;
  428. if (!pd) {
  429. pd = &default_i2c_data;
  430. pd->bus_num = 0;
  431. }
  432. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  433. &s3c_device_i2c0);
  434. if (!npd->cfg_gpio)
  435. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  436. }
  437. #ifdef CONFIG_S3C_DEV_I2C1
  438. static struct resource s3c_i2c1_resource[] = {
  439. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  440. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  441. };
  442. struct platform_device s3c_device_i2c1 = {
  443. .name = "s3c2410-i2c",
  444. .id = 1,
  445. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  446. .resource = s3c_i2c1_resource,
  447. };
  448. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  449. {
  450. struct s3c2410_platform_i2c *npd;
  451. if (!pd) {
  452. pd = &default_i2c_data;
  453. pd->bus_num = 1;
  454. }
  455. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  456. &s3c_device_i2c1);
  457. if (!npd->cfg_gpio)
  458. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  459. }
  460. #endif /* CONFIG_S3C_DEV_I2C1 */
  461. #ifdef CONFIG_S3C_DEV_I2C2
  462. static struct resource s3c_i2c2_resource[] = {
  463. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  464. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  465. };
  466. struct platform_device s3c_device_i2c2 = {
  467. .name = "s3c2410-i2c",
  468. .id = 2,
  469. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  470. .resource = s3c_i2c2_resource,
  471. };
  472. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  473. {
  474. struct s3c2410_platform_i2c *npd;
  475. if (!pd) {
  476. pd = &default_i2c_data;
  477. pd->bus_num = 2;
  478. }
  479. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  480. &s3c_device_i2c2);
  481. if (!npd->cfg_gpio)
  482. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  483. }
  484. #endif /* CONFIG_S3C_DEV_I2C2 */
  485. #ifdef CONFIG_S3C_DEV_I2C3
  486. static struct resource s3c_i2c3_resource[] = {
  487. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  488. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  489. };
  490. struct platform_device s3c_device_i2c3 = {
  491. .name = "s3c2440-i2c",
  492. .id = 3,
  493. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  494. .resource = s3c_i2c3_resource,
  495. };
  496. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  497. {
  498. struct s3c2410_platform_i2c *npd;
  499. if (!pd) {
  500. pd = &default_i2c_data;
  501. pd->bus_num = 3;
  502. }
  503. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  504. &s3c_device_i2c3);
  505. if (!npd->cfg_gpio)
  506. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  507. }
  508. #endif /*CONFIG_S3C_DEV_I2C3 */
  509. #ifdef CONFIG_S3C_DEV_I2C4
  510. static struct resource s3c_i2c4_resource[] = {
  511. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  512. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  513. };
  514. struct platform_device s3c_device_i2c4 = {
  515. .name = "s3c2440-i2c",
  516. .id = 4,
  517. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  518. .resource = s3c_i2c4_resource,
  519. };
  520. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  521. {
  522. struct s3c2410_platform_i2c *npd;
  523. if (!pd) {
  524. pd = &default_i2c_data;
  525. pd->bus_num = 4;
  526. }
  527. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  528. &s3c_device_i2c4);
  529. if (!npd->cfg_gpio)
  530. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  531. }
  532. #endif /*CONFIG_S3C_DEV_I2C4 */
  533. #ifdef CONFIG_S3C_DEV_I2C5
  534. static struct resource s3c_i2c5_resource[] = {
  535. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  536. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  537. };
  538. struct platform_device s3c_device_i2c5 = {
  539. .name = "s3c2440-i2c",
  540. .id = 5,
  541. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  542. .resource = s3c_i2c5_resource,
  543. };
  544. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  545. {
  546. struct s3c2410_platform_i2c *npd;
  547. if (!pd) {
  548. pd = &default_i2c_data;
  549. pd->bus_num = 5;
  550. }
  551. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  552. &s3c_device_i2c5);
  553. if (!npd->cfg_gpio)
  554. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  555. }
  556. #endif /*CONFIG_S3C_DEV_I2C5 */
  557. #ifdef CONFIG_S3C_DEV_I2C6
  558. static struct resource s3c_i2c6_resource[] = {
  559. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  560. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  561. };
  562. struct platform_device s3c_device_i2c6 = {
  563. .name = "s3c2440-i2c",
  564. .id = 6,
  565. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  566. .resource = s3c_i2c6_resource,
  567. };
  568. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  569. {
  570. struct s3c2410_platform_i2c *npd;
  571. if (!pd) {
  572. pd = &default_i2c_data;
  573. pd->bus_num = 6;
  574. }
  575. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  576. &s3c_device_i2c6);
  577. if (!npd->cfg_gpio)
  578. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  579. }
  580. #endif /* CONFIG_S3C_DEV_I2C6 */
  581. #ifdef CONFIG_S3C_DEV_I2C7
  582. static struct resource s3c_i2c7_resource[] = {
  583. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  584. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  585. };
  586. struct platform_device s3c_device_i2c7 = {
  587. .name = "s3c2440-i2c",
  588. .id = 7,
  589. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  590. .resource = s3c_i2c7_resource,
  591. };
  592. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  593. {
  594. struct s3c2410_platform_i2c *npd;
  595. if (!pd) {
  596. pd = &default_i2c_data;
  597. pd->bus_num = 7;
  598. }
  599. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  600. &s3c_device_i2c7);
  601. if (!npd->cfg_gpio)
  602. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  603. }
  604. #endif /* CONFIG_S3C_DEV_I2C7 */
  605. /* I2C HDMIPHY */
  606. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  607. static struct resource s5p_i2c_resource[] = {
  608. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  609. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  610. };
  611. struct platform_device s5p_device_i2c_hdmiphy = {
  612. .name = "s3c2440-hdmiphy-i2c",
  613. .id = -1,
  614. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  615. .resource = s5p_i2c_resource,
  616. };
  617. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  618. {
  619. struct s3c2410_platform_i2c *npd;
  620. if (!pd) {
  621. pd = &default_i2c_data;
  622. if (soc_is_exynos4210() ||
  623. soc_is_exynos4212() || soc_is_exynos4412())
  624. pd->bus_num = 8;
  625. else if (soc_is_s5pv210())
  626. pd->bus_num = 3;
  627. else
  628. pd->bus_num = 0;
  629. }
  630. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  631. &s5p_device_i2c_hdmiphy);
  632. }
  633. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  634. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  635. struct i2c_board_info *mhl_info, int mhl_bus)
  636. {
  637. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  638. if (soc_is_exynos4210() ||
  639. soc_is_exynos4212() || soc_is_exynos4412())
  640. pd->hdmiphy_bus = 8;
  641. else if (soc_is_s5pv210())
  642. pd->hdmiphy_bus = 3;
  643. else
  644. pd->hdmiphy_bus = 0;
  645. pd->hdmiphy_info = hdmiphy_info;
  646. pd->mhl_info = mhl_info;
  647. pd->mhl_bus = mhl_bus;
  648. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  649. &s5p_device_hdmi);
  650. }
  651. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  652. /* I2S */
  653. #ifdef CONFIG_PLAT_S3C24XX
  654. static struct resource s3c_iis_resource[] = {
  655. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  656. };
  657. struct platform_device s3c_device_iis = {
  658. .name = "s3c24xx-iis",
  659. .id = -1,
  660. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  661. .resource = s3c_iis_resource,
  662. .dev = {
  663. .dma_mask = &samsung_device_dma_mask,
  664. .coherent_dma_mask = DMA_BIT_MASK(32),
  665. }
  666. };
  667. #endif /* CONFIG_PLAT_S3C24XX */
  668. /* IDE CFCON */
  669. #ifdef CONFIG_SAMSUNG_DEV_IDE
  670. static struct resource s3c_cfcon_resource[] = {
  671. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  672. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  673. };
  674. struct platform_device s3c_device_cfcon = {
  675. .id = 0,
  676. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  677. .resource = s3c_cfcon_resource,
  678. };
  679. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  680. {
  681. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  682. &s3c_device_cfcon);
  683. }
  684. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  685. /* KEYPAD */
  686. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  687. static struct resource samsung_keypad_resources[] = {
  688. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  689. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  690. };
  691. struct platform_device samsung_device_keypad = {
  692. .name = "samsung-keypad",
  693. .id = -1,
  694. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  695. .resource = samsung_keypad_resources,
  696. };
  697. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  698. {
  699. struct samsung_keypad_platdata *npd;
  700. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  701. &samsung_device_keypad);
  702. if (!npd->cfg_gpio)
  703. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  704. }
  705. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  706. /* LCD Controller */
  707. #ifdef CONFIG_PLAT_S3C24XX
  708. static struct resource s3c_lcd_resource[] = {
  709. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  710. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  711. };
  712. struct platform_device s3c_device_lcd = {
  713. .name = "s3c2410-lcd",
  714. .id = -1,
  715. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  716. .resource = s3c_lcd_resource,
  717. .dev = {
  718. .dma_mask = &samsung_device_dma_mask,
  719. .coherent_dma_mask = DMA_BIT_MASK(32),
  720. }
  721. };
  722. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  723. {
  724. struct s3c2410fb_mach_info *npd;
  725. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  726. if (npd) {
  727. npd->displays = kmemdup(pd->displays,
  728. sizeof(struct s3c2410fb_display) * npd->num_displays,
  729. GFP_KERNEL);
  730. if (!npd->displays)
  731. printk(KERN_ERR "no memory for LCD display data\n");
  732. } else {
  733. printk(KERN_ERR "no memory for LCD platform data\n");
  734. }
  735. }
  736. #endif /* CONFIG_PLAT_S3C24XX */
  737. /* MFC */
  738. #ifdef CONFIG_S5P_DEV_MFC
  739. static struct resource s5p_mfc_resource[] = {
  740. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  741. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  742. };
  743. struct platform_device s5p_device_mfc = {
  744. .name = "s5p-mfc",
  745. .id = -1,
  746. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  747. .resource = s5p_mfc_resource,
  748. };
  749. /*
  750. * MFC hardware has 2 memory interfaces which are modelled as two separate
  751. * platform devices to let dma-mapping distinguish between them.
  752. *
  753. * MFC parent device (s5p_device_mfc) must be registered before memory
  754. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  755. */
  756. struct platform_device s5p_device_mfc_l = {
  757. .name = "s5p-mfc-l",
  758. .id = -1,
  759. .dev = {
  760. .parent = &s5p_device_mfc.dev,
  761. .dma_mask = &samsung_device_dma_mask,
  762. .coherent_dma_mask = DMA_BIT_MASK(32),
  763. },
  764. };
  765. struct platform_device s5p_device_mfc_r = {
  766. .name = "s5p-mfc-r",
  767. .id = -1,
  768. .dev = {
  769. .parent = &s5p_device_mfc.dev,
  770. .dma_mask = &samsung_device_dma_mask,
  771. .coherent_dma_mask = DMA_BIT_MASK(32),
  772. },
  773. };
  774. #endif /* CONFIG_S5P_DEV_MFC */
  775. /* MIPI CSIS */
  776. #ifdef CONFIG_S5P_DEV_CSIS0
  777. static struct resource s5p_mipi_csis0_resource[] = {
  778. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  779. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  780. };
  781. struct platform_device s5p_device_mipi_csis0 = {
  782. .name = "s5p-mipi-csis",
  783. .id = 0,
  784. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  785. .resource = s5p_mipi_csis0_resource,
  786. };
  787. #endif /* CONFIG_S5P_DEV_CSIS0 */
  788. #ifdef CONFIG_S5P_DEV_CSIS1
  789. static struct resource s5p_mipi_csis1_resource[] = {
  790. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  791. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  792. };
  793. struct platform_device s5p_device_mipi_csis1 = {
  794. .name = "s5p-mipi-csis",
  795. .id = 1,
  796. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  797. .resource = s5p_mipi_csis1_resource,
  798. };
  799. #endif
  800. /* NAND */
  801. #ifdef CONFIG_S3C_DEV_NAND
  802. static struct resource s3c_nand_resource[] = {
  803. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  804. };
  805. struct platform_device s3c_device_nand = {
  806. .name = "s3c2410-nand",
  807. .id = -1,
  808. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  809. .resource = s3c_nand_resource,
  810. };
  811. /*
  812. * s3c_nand_copy_set() - copy nand set data
  813. * @set: The new structure, directly copied from the old.
  814. *
  815. * Copy all the fields from the NAND set field from what is probably __initdata
  816. * to new kernel memory. The code returns 0 if the copy happened correctly or
  817. * an error code for the calling function to display.
  818. *
  819. * Note, we currently do not try and look to see if we've already copied the
  820. * data in a previous set.
  821. */
  822. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  823. {
  824. void *ptr;
  825. int size;
  826. size = sizeof(struct mtd_partition) * set->nr_partitions;
  827. if (size) {
  828. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  829. set->partitions = ptr;
  830. if (!ptr)
  831. return -ENOMEM;
  832. }
  833. if (set->nr_map && set->nr_chips) {
  834. size = sizeof(int) * set->nr_chips;
  835. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  836. set->nr_map = ptr;
  837. if (!ptr)
  838. return -ENOMEM;
  839. }
  840. if (set->ecc_layout) {
  841. ptr = kmemdup(set->ecc_layout,
  842. sizeof(struct nand_ecclayout), GFP_KERNEL);
  843. set->ecc_layout = ptr;
  844. if (!ptr)
  845. return -ENOMEM;
  846. }
  847. return 0;
  848. }
  849. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  850. {
  851. struct s3c2410_platform_nand *npd;
  852. int size;
  853. int ret;
  854. /* note, if we get a failure in allocation, we simply drop out of the
  855. * function. If there is so little memory available at initialisation
  856. * time then there is little chance the system is going to run.
  857. */
  858. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  859. &s3c_device_nand);
  860. if (!npd)
  861. return;
  862. /* now see if we need to copy any of the nand set data */
  863. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  864. if (size) {
  865. struct s3c2410_nand_set *from = npd->sets;
  866. struct s3c2410_nand_set *to;
  867. int i;
  868. to = kmemdup(from, size, GFP_KERNEL);
  869. npd->sets = to; /* set, even if we failed */
  870. if (!to) {
  871. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  872. return;
  873. }
  874. for (i = 0; i < npd->nr_sets; i++) {
  875. ret = s3c_nand_copy_set(to);
  876. if (ret) {
  877. printk(KERN_ERR "%s: failed to copy set %d\n",
  878. __func__, i);
  879. return;
  880. }
  881. to++;
  882. }
  883. }
  884. }
  885. #endif /* CONFIG_S3C_DEV_NAND */
  886. /* ONENAND */
  887. #ifdef CONFIG_S3C_DEV_ONENAND
  888. static struct resource s3c_onenand_resources[] = {
  889. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  890. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  891. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  892. };
  893. struct platform_device s3c_device_onenand = {
  894. .name = "samsung-onenand",
  895. .id = 0,
  896. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  897. .resource = s3c_onenand_resources,
  898. };
  899. #endif /* CONFIG_S3C_DEV_ONENAND */
  900. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  901. static struct resource s3c64xx_onenand1_resources[] = {
  902. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  903. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  904. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  905. };
  906. struct platform_device s3c64xx_device_onenand1 = {
  907. .name = "samsung-onenand",
  908. .id = 1,
  909. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  910. .resource = s3c64xx_onenand1_resources,
  911. };
  912. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  913. {
  914. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  915. &s3c64xx_device_onenand1);
  916. }
  917. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  918. #ifdef CONFIG_S5P_DEV_ONENAND
  919. static struct resource s5p_onenand_resources[] = {
  920. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  921. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  922. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  923. };
  924. struct platform_device s5p_device_onenand = {
  925. .name = "s5pc110-onenand",
  926. .id = -1,
  927. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  928. .resource = s5p_onenand_resources,
  929. };
  930. #endif /* CONFIG_S5P_DEV_ONENAND */
  931. /* PMU */
  932. #ifdef CONFIG_PLAT_S5P
  933. static struct resource s5p_pmu_resource[] = {
  934. DEFINE_RES_IRQ(IRQ_PMU)
  935. };
  936. static struct platform_device s5p_device_pmu = {
  937. .name = "arm-pmu",
  938. .id = -1,
  939. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  940. .resource = s5p_pmu_resource,
  941. };
  942. static int __init s5p_pmu_init(void)
  943. {
  944. platform_device_register(&s5p_device_pmu);
  945. return 0;
  946. }
  947. arch_initcall(s5p_pmu_init);
  948. #endif /* CONFIG_PLAT_S5P */
  949. /* PWM Timer */
  950. #ifdef CONFIG_SAMSUNG_DEV_PWM
  951. #define TIMER_RESOURCE_SIZE (1)
  952. #define TIMER_RESOURCE(_tmr, _irq) \
  953. (struct resource [TIMER_RESOURCE_SIZE]) { \
  954. [0] = { \
  955. .start = _irq, \
  956. .end = _irq, \
  957. .flags = IORESOURCE_IRQ \
  958. } \
  959. }
  960. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  961. .name = "s3c24xx-pwm", \
  962. .id = _tmr_no, \
  963. .num_resources = TIMER_RESOURCE_SIZE, \
  964. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  965. /*
  966. * since we already have an static mapping for the timer,
  967. * we do not bother setting any IO resource for the base.
  968. */
  969. struct platform_device s3c_device_timer[] = {
  970. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  971. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  972. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  973. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  974. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  975. };
  976. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  977. /* RTC */
  978. #ifdef CONFIG_PLAT_S3C24XX
  979. static struct resource s3c_rtc_resource[] = {
  980. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  981. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  982. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  983. };
  984. struct platform_device s3c_device_rtc = {
  985. .name = "s3c2410-rtc",
  986. .id = -1,
  987. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  988. .resource = s3c_rtc_resource,
  989. };
  990. #endif /* CONFIG_PLAT_S3C24XX */
  991. #ifdef CONFIG_S3C_DEV_RTC
  992. static struct resource s3c_rtc_resource[] = {
  993. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  994. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  995. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  996. };
  997. struct platform_device s3c_device_rtc = {
  998. .name = "s3c64xx-rtc",
  999. .id = -1,
  1000. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1001. .resource = s3c_rtc_resource,
  1002. };
  1003. #endif /* CONFIG_S3C_DEV_RTC */
  1004. /* SDI */
  1005. #ifdef CONFIG_PLAT_S3C24XX
  1006. static struct resource s3c_sdi_resource[] = {
  1007. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1008. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1009. };
  1010. struct platform_device s3c_device_sdi = {
  1011. .name = "s3c2410-sdi",
  1012. .id = -1,
  1013. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1014. .resource = s3c_sdi_resource,
  1015. };
  1016. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1017. {
  1018. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1019. &s3c_device_sdi);
  1020. }
  1021. #endif /* CONFIG_PLAT_S3C24XX */
  1022. /* SPI */
  1023. #ifdef CONFIG_PLAT_S3C24XX
  1024. static struct resource s3c_spi0_resource[] = {
  1025. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1026. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1027. };
  1028. struct platform_device s3c_device_spi0 = {
  1029. .name = "s3c2410-spi",
  1030. .id = 0,
  1031. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1032. .resource = s3c_spi0_resource,
  1033. .dev = {
  1034. .dma_mask = &samsung_device_dma_mask,
  1035. .coherent_dma_mask = DMA_BIT_MASK(32),
  1036. }
  1037. };
  1038. static struct resource s3c_spi1_resource[] = {
  1039. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1040. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1041. };
  1042. struct platform_device s3c_device_spi1 = {
  1043. .name = "s3c2410-spi",
  1044. .id = 1,
  1045. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1046. .resource = s3c_spi1_resource,
  1047. .dev = {
  1048. .dma_mask = &samsung_device_dma_mask,
  1049. .coherent_dma_mask = DMA_BIT_MASK(32),
  1050. }
  1051. };
  1052. #endif /* CONFIG_PLAT_S3C24XX */
  1053. /* Touchscreen */
  1054. #ifdef CONFIG_PLAT_S3C24XX
  1055. static struct resource s3c_ts_resource[] = {
  1056. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1057. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1058. };
  1059. struct platform_device s3c_device_ts = {
  1060. .name = "s3c2410-ts",
  1061. .id = -1,
  1062. .dev.parent = &s3c_device_adc.dev,
  1063. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1064. .resource = s3c_ts_resource,
  1065. };
  1066. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1067. {
  1068. s3c_set_platdata(hard_s3c2410ts_info,
  1069. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1070. }
  1071. #endif /* CONFIG_PLAT_S3C24XX */
  1072. #ifdef CONFIG_SAMSUNG_DEV_TS
  1073. static struct resource s3c_ts_resource[] = {
  1074. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1075. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1076. };
  1077. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1078. .delay = 10000,
  1079. .presc = 49,
  1080. .oversampling_shift = 2,
  1081. };
  1082. struct platform_device s3c_device_ts = {
  1083. .name = "s3c64xx-ts",
  1084. .id = -1,
  1085. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1086. .resource = s3c_ts_resource,
  1087. };
  1088. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1089. {
  1090. if (!pd)
  1091. pd = &default_ts_data;
  1092. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1093. &s3c_device_ts);
  1094. }
  1095. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1096. /* TV */
  1097. #ifdef CONFIG_S5P_DEV_TV
  1098. static struct resource s5p_hdmi_resources[] = {
  1099. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1100. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1101. };
  1102. struct platform_device s5p_device_hdmi = {
  1103. .name = "s5p-hdmi",
  1104. .id = -1,
  1105. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1106. .resource = s5p_hdmi_resources,
  1107. };
  1108. static struct resource s5p_sdo_resources[] = {
  1109. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1110. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1111. };
  1112. struct platform_device s5p_device_sdo = {
  1113. .name = "s5p-sdo",
  1114. .id = -1,
  1115. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1116. .resource = s5p_sdo_resources,
  1117. };
  1118. static struct resource s5p_mixer_resources[] = {
  1119. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1120. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1121. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1122. };
  1123. struct platform_device s5p_device_mixer = {
  1124. .name = "s5p-mixer",
  1125. .id = -1,
  1126. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1127. .resource = s5p_mixer_resources,
  1128. .dev = {
  1129. .dma_mask = &samsung_device_dma_mask,
  1130. .coherent_dma_mask = DMA_BIT_MASK(32),
  1131. }
  1132. };
  1133. #endif /* CONFIG_S5P_DEV_TV */
  1134. /* USB */
  1135. #ifdef CONFIG_S3C_DEV_USB_HOST
  1136. static struct resource s3c_usb_resource[] = {
  1137. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1138. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1139. };
  1140. struct platform_device s3c_device_ohci = {
  1141. .name = "s3c2410-ohci",
  1142. .id = -1,
  1143. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1144. .resource = s3c_usb_resource,
  1145. .dev = {
  1146. .dma_mask = &samsung_device_dma_mask,
  1147. .coherent_dma_mask = DMA_BIT_MASK(32),
  1148. }
  1149. };
  1150. /*
  1151. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1152. * @info: The platform data.
  1153. *
  1154. * This call copies the @info passed in and sets the device .platform_data
  1155. * field to that copy. The @info is copied so that the original can be marked
  1156. * __initdata.
  1157. */
  1158. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1159. {
  1160. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1161. &s3c_device_ohci);
  1162. }
  1163. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1164. /* USB Device (Gadget) */
  1165. #ifdef CONFIG_PLAT_S3C24XX
  1166. static struct resource s3c_usbgadget_resource[] = {
  1167. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1168. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1169. };
  1170. struct platform_device s3c_device_usbgadget = {
  1171. .name = "s3c2410-usbgadget",
  1172. .id = -1,
  1173. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1174. .resource = s3c_usbgadget_resource,
  1175. };
  1176. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1177. {
  1178. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1179. }
  1180. #endif /* CONFIG_PLAT_S3C24XX */
  1181. /* USB EHCI Host Controller */
  1182. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1183. static struct resource s5p_ehci_resource[] = {
  1184. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1185. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1186. };
  1187. struct platform_device s5p_device_ehci = {
  1188. .name = "s5p-ehci",
  1189. .id = -1,
  1190. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1191. .resource = s5p_ehci_resource,
  1192. .dev = {
  1193. .dma_mask = &samsung_device_dma_mask,
  1194. .coherent_dma_mask = DMA_BIT_MASK(32),
  1195. }
  1196. };
  1197. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1198. {
  1199. struct s5p_ehci_platdata *npd;
  1200. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1201. &s5p_device_ehci);
  1202. if (!npd->phy_init)
  1203. npd->phy_init = s5p_usb_phy_init;
  1204. if (!npd->phy_exit)
  1205. npd->phy_exit = s5p_usb_phy_exit;
  1206. }
  1207. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1208. /* USB HSOTG */
  1209. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1210. static struct resource s3c_usb_hsotg_resources[] = {
  1211. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1212. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1213. };
  1214. struct platform_device s3c_device_usb_hsotg = {
  1215. .name = "s3c-hsotg",
  1216. .id = -1,
  1217. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1218. .resource = s3c_usb_hsotg_resources,
  1219. .dev = {
  1220. .dma_mask = &samsung_device_dma_mask,
  1221. .coherent_dma_mask = DMA_BIT_MASK(32),
  1222. },
  1223. };
  1224. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1225. {
  1226. struct s3c_hsotg_plat *npd;
  1227. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1228. &s3c_device_usb_hsotg);
  1229. if (!npd->phy_init)
  1230. npd->phy_init = s5p_usb_phy_init;
  1231. if (!npd->phy_exit)
  1232. npd->phy_exit = s5p_usb_phy_exit;
  1233. }
  1234. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1235. /* USB High Spped 2.0 Device (Gadget) */
  1236. #ifdef CONFIG_PLAT_S3C24XX
  1237. static struct resource s3c_hsudc_resource[] = {
  1238. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1239. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1240. };
  1241. struct platform_device s3c_device_usb_hsudc = {
  1242. .name = "s3c-hsudc",
  1243. .id = -1,
  1244. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1245. .resource = s3c_hsudc_resource,
  1246. .dev = {
  1247. .dma_mask = &samsung_device_dma_mask,
  1248. .coherent_dma_mask = DMA_BIT_MASK(32),
  1249. },
  1250. };
  1251. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1252. {
  1253. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1254. }
  1255. #endif /* CONFIG_PLAT_S3C24XX */
  1256. /* WDT */
  1257. #ifdef CONFIG_S3C_DEV_WDT
  1258. static struct resource s3c_wdt_resource[] = {
  1259. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1260. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1261. };
  1262. struct platform_device s3c_device_wdt = {
  1263. .name = "s3c2410-wdt",
  1264. .id = -1,
  1265. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1266. .resource = s3c_wdt_resource,
  1267. };
  1268. #endif /* CONFIG_S3C_DEV_WDT */
  1269. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1270. static struct resource s3c64xx_spi0_resource[] = {
  1271. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1272. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1273. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1274. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1275. };
  1276. struct platform_device s3c64xx_device_spi0 = {
  1277. .name = "s3c6410-spi",
  1278. .id = 0,
  1279. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1280. .resource = s3c64xx_spi0_resource,
  1281. .dev = {
  1282. .dma_mask = &samsung_device_dma_mask,
  1283. .coherent_dma_mask = DMA_BIT_MASK(32),
  1284. },
  1285. };
  1286. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1287. int num_cs)
  1288. {
  1289. struct s3c64xx_spi_info pd;
  1290. /* Reject invalid configuration */
  1291. if (!num_cs || src_clk_nr < 0) {
  1292. pr_err("%s: Invalid SPI configuration\n", __func__);
  1293. return;
  1294. }
  1295. pd.num_cs = num_cs;
  1296. pd.src_clk_nr = src_clk_nr;
  1297. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1298. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1299. }
  1300. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1301. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1302. static struct resource s3c64xx_spi1_resource[] = {
  1303. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1304. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),