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waterDataStatistics
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dataSharedMemory
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memoryCall.h

memoryCall.h 6.1 KB
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  1. /*
    2. 

  2.  * Copyright 2011 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF60X_H
    8. 

  8. #define _CDEF_BF60X_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
    15. 

  15. 

  16. #define bfin_read_CHIPID()		bfin_read32(CHIPID)
    17. 

  17. #define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
    18. 

  18. 

  19. /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
    20. 

  20. 

  21. /* SEC0 Registers */
    22. 

  22. #define bfin_read_SEC0_CCTL()		bfin_read32(SEC0_CCTL)
    23. 

  23. #define bfin_write_SEC0_CCTL(val)	bfin_write32(SEC0_CCTL, val)
    24. 

  24. #define bfin_read_SEC0_CSID()		bfin_read32(SEC0_CSID)
    25. 

  25. #define bfin_write_SEC0_CSID(val)	bfin_write32(SEC0_CSID, val)
    26. 

  26. #define bfin_read_SEC_GCTL()		bfin_read32(SEC_GCTL)
    27. 

  27. #define bfin_write_SEC_GCTL(val)	bfin_write32(SEC_GCTL, val)
    28. 

  28. 

  29. #define bfin_read_SEC_FCTL()		bfin_read32(SEC_FCTL)
    30. 

  30. #define bfin_write_SEC_FCTL(val)	bfin_write32(SEC_FCTL, val)
    31. 

  31. 

  32. #define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC_SCTL0 + (sid) * 8))
    33. 

  33. #define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC_SCTL0 + (sid) * 8), val)
    34. 

  34. 

  35. #define bfin_read_SEC_SSTAT(sid)	bfin_read32((SEC_SSTAT0 + (sid) * 8))
    36. 

  36. #define bfin_write_SEC_SSTAT(sid, val)	bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
    37. 

  37. 

  38. /* RCU0 Registers */
    39. 

  39. #define bfin_read_RCU0_CTL()		bfin_read32(RCU0_CTL)
    40. 

  40. #define bfin_write_RCU0_CTL(val)	bfin_write32(RCU0_CTL, val)
    41. 

  41. 

  42. /* Watchdog Timer Registers */
    43. 

  43. #define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
    44. 

  44. #define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
    45. 

  45. #define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
    46. 

  46. #define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
    47. 

  47. #define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
    48. 

  48. #define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)
    49. 

  49. 

  50. /* RTC Registers */
    51. 

  51. 

  52. /* UART0 Registers */
    53. 

  53. 

  54. #define bfin_read_UART0_REVID()		bfin_read32(UART0_REVID)
    55. 

  55. #define bfin_write_UART0_REVID(val)	bfin_write32(UART0_REVID, val)
    56. 

  56. #define bfin_read_UART0_GCTL()		bfin_read32(UART0_GCTL)
    57. 

  57. #define bfin_write_UART0_GCTL(val)	bfin_write32(UART0_GCTL, val)
    58. 

  58. #define bfin_read_UART0_STAT()		bfin_read32(UART0_STAT)
    59. 

  59. #define bfin_write_UART0_STAT(val)	bfin_write32(UART0_STAT, val)
    60. 

  60. #define bfin_read_UART0_SCR()		bfin_read32(UART0_SCR)
    61. 

  61. #define bfin_write_UART0_SCR(val)	bfin_write32(UART0_SCR, val)
    62. 

  62. #define bfin_read_UART0_CLK()		bfin_read32(UART0_CLK)
    63. 

  63. #define bfin_write_UART0_CLK(val)	bfin_write32(UART0_CLK, val)
    64. 

  64. #define bfin_read_UART0_IER()		bfin_read32(UART0_IER)
    65. 

  65. #define bfin_write_UART0_IER(val)	bfin_write32(UART0_IER, val)
    66. 

  66. #define bfin_read_UART0_IER_SET()	bfin_read32(UART0_IER_SET)
    67. 

  67. #define bfin_write_UART0_IER_SET(val)	bfin_write32(UART0_IER_SET, val)
    68. 

  68. #define bfin_read_UART0_IER_CLEAR()	bfin_read32(UART0_IER_CLEAR)
    69. 

  69. #define bfin_write_UART0_IER_CLEAR(val)	bfin_write32(UART0_IER_CLEAR, val)
    70. 

  70. #define bfin_read_UART0_RBR()		bfin_read32(UART0_RBR)
    71. 

  71. #define bfin_write_UART0_RBR(val)	bfin_write32(UART0_RBR, val)
    72. 

  72. #define bfin_read_UART0_THR()		bfin_read32(UART0_THR)
    73. 

  73. #define bfin_write_UART0_THR(val)	bfin_write32(UART0_THR, val)
    74. 

  74. #define bfin_read_UART0_TAIP()		bfin_read32(UART0_TAIP)
    75. 

  75. #define bfin_write_UART0_TAIP(val)	bfin_write32(UART0_TAIP, val)
    76. 

  76. #define bfin_read_UART0_TSR()		bfin_read32(UART0_TSR)
    77. 

  77. #define bfin_write_UART0_TSR(val)	bfin_write32(UART0_TSR, val)
    78. 

  78. #define bfin_read_UART0_RSR()		bfin_read32(UART0_RSR)
    79. 

  79. #define bfin_write_UART0_RSR(val)	bfin_write32(UART0_RSR, val)
    80. 

  80. #define bfin_read_UART0_TXCNT()		bfin_read32(UART0_TXCNT)
    81. 

  81. #define bfin_write_UART0_TXCNT(val)	bfin_write32(UART0_TXCNT, val)
    82. 

  82. #define bfin_read_UART0_RXCNT()		bfin_read32(UART0_RXCNT)
    83. 

  83. #define bfin_write_UART0_RXCNT(val)	bfin_write32(UART0_RXCNT, val)
    84. 

  84. 

  85. /* UART1 Registers */
    86. 

  86. 

  87. #define bfin_read_UART1_REVID()		bfin_read32(UART1_REVID)
    88. 

  88. #define bfin_write_UART1_REVID(val)	bfin_write32(UART1_REVID, val)
    89. 

  89. #define bfin_read_UART1_GCTL()		bfin_read32(UART1_GCTL)
    90. 

  90. #define bfin_write_UART1_GCTL(val)	bfin_write32(UART1_GCTL, val)
    91. 

  91. #define bfin_read_UART1_STAT()		bfin_read32(UART1_STAT)
    92. 

  92. #define bfin_write_UART1_STAT(val)	bfin_write32(UART1_STAT, val)
    93. 

  93. #define bfin_read_UART1_SCR()		bfin_read32(UART1_SCR)
    94. 

  94. #define bfin_write_UART1_SCR(val)	bfin_write32(UART1_SCR, val)
    95. 

  95. #define bfin_read_UART1_CLK()		bfin_read32(UART1_CLK)
    96. 

  96. #define bfin_write_UART1_CLK(val)	bfin_write32(UART1_CLK, val)
    97. 

  97. #define bfin_read_UART1_IER()		bfin_read32(UART1_IER)
    98. 

  98. #define bfin_write_UART1_IER(val)	bfin_write32(UART1_IER, val)
    99. 

  99. #define bfin_read_UART1_IER_SET()	bfin_read32(UART1_IER_SET)
    100. 

  100. #define bfin_write_UART1_IER_SET(val)	bfin_write32(UART1_IER_SET, val)
    101. 

  101. #define bfin_read_UART1_IER_CLEAR()	bfin_read32(UART1_IER_CLEAR)
    102. 

  102. #define bfin_write_UART1_IER_CLEAR(val)	bfin_write32(UART1_IER_CLEAR, val)
    103. 

  103. #define bfin_read_UART1_RBR()		bfin_read32(UART1_RBR)
    104. 

  104. #define bfin_write_UART1_RBR(val)	bfin_write32(UART1_RBR, val)
    105. 

  105. #define bfin_read_UART1_THR()		bfin_read32(UART1_THR)
    106. 

  106. #define bfin_write_UART1_THR(val)	bfin_write32(UART1_THR, val)
    107. 

  107. #define bfin_read_UART1_TAIP()		bfin_read32(UART1_TAIP)
    108. 

  108. #define bfin_write_UART1_TAIP(val)	bfin_write32(UART1_TAIP, val)
    109. 

  109. #define bfin_read_UART1_TSR()		bfin_read32(UART1_TSR)
    110. 

  110. #define bfin_write_UART1_TSR(val)	bfin_write32(UART1_TSR, val)
    111. 

  111. #define bfin_read_UART1_RSR()		bfin_read32(UART1_RSR)
    112. 

  112. #define bfin_write_UART1_RSR(val)	bfin_write32(UART1_RSR, val)
    113. 

  113. #define bfin_read_UART1_TXCNT()		bfin_read32(UART1_TXCNT)
    114. 

  114. #define bfin_write_UART1_TXCNT(val)	bfin_write32(UART1_TXCNT, val)
    115. 

  115. #define bfin_read_UART1_RXCNT()		bfin_read32(UART1_RXCNT)
    116. 

  116. #define bfin_write_UART1_RXCNT(val)	bfin_write32(UART1_RXCNT, val)
    117. 

  117. 

  118. 

  119. /* SPI0 Registers */
    120. 

  120. 

  121. #define bfin_read_SPI0_CTL()		bfin_read32(SPI0_CTL)
    122. 

  122. #define bfin_write_SPI0_CTL(val)	bfin_write32(SPI0_CTL, val)
    123. 

  123. #define bfin_read_SPI0_RXCTL()		bfin_read32(SPI0_RXCTL)
    124. 

  124. #define bfin_write_SPI0_RXCTL(val)	bfin_write32(SPI0_RXCTL, val)
    125. 

  125. #define bfin_read_SPI0_TXCTL()		bfin_read32(SPI0_TXCTL)
    126. 

  126. #define bfin_write_SPI0_TXCTL(val)	bfin_write32(SPI0_TXCTL, val)
    127. 

  127. #define bfin_read_SPI0_CLK()		bfin_read32(SPI0_CLK)
    128. 

  128. #define bfin_write_SPI0_CLK(val)	bfin_write32(SPI0_CLK, val)
    129. 

  129. #define bfin_read_SPI0_DLY()		bfin_read32(SPI0_DLY)
    130. 

  130. #define bfin_write_SPI0_DLY(val)	bfin_write32(SPI0_DLY, val)
    131. 

  131. #define bfin_read_SPI0_SLVSEL()		bfin_read32(SPI0_SLVSEL)
    132.