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alarmProcessingDataOperation.h

alarmProcessingDataOperation.h 7.2 KB
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  1. #ifndef __MACH_MX53_H__
    2. 

  2. #define __MACH_MX53_H__
    3. 

  3. 

  4. /*
    5. 

  5.  * IROM
    6. 

  6.  */
    7. 

  7. #define MX53_IROM_BASE_ADDR		0x0
    8. 

  8. #define MX53_IROM_SIZE			SZ_64K
    9. 

  9. 

  10. /* TZIC */
    11. 

  11. #define MX53_TZIC_BASE_ADDR		0x0FFFC000
    12. 

  12. #define MX53_TZIC_SIZE			SZ_16K
    13. 

  13. 

  14. /*
    15. 

  15.  * AHCI SATA
    16. 

  16.  */
    17. 

  17. #define MX53_SATA_BASE_ADDR		0x10000000
    18. 

  18. 

  19. /*
    20. 

  20.  * NFC
    21. 

  21.  */
    22. 

  22. #define MX53_NFC_AXI_BASE_ADDR	0xF7FF0000	/* NAND flash AXI */
    23. 

  23. #define MX53_NFC_AXI_SIZE		SZ_64K
    24. 

  24. 

  25. /*
    26. 

  26.  * IRAM
    27. 

  27.  */
    28. 

  28. #define MX53_IRAM_BASE_ADDR	0xF8000000	/* internal ram */
    29. 

  29. #define MX53_IRAM_PARTITIONS	16
    30. 

  30. #define MX53_IRAM_SIZE		(MX53_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
    31. 

  31. 

  32. /*
    33. 

  33.  * Graphics Memory of GPU
    34. 

  34.  */
    35. 

  35. #define MX53_IPU_CTRL_BASE_ADDR	0x18000000
    36. 

  36. #define MX53_GPU2D_BASE_ADDR		0x20000000
    37. 

  37. #define MX53_GPU_BASE_ADDR		0x30000000
    38. 

  38. #define MX53_GPU_GMEM_BASE_ADDR	0xF8020000
    39. 

  39. 

  40. #define MX53_DEBUG_BASE_ADDR		0x40000000
    41. 

  41. #define MX53_DEBUG_SIZE		SZ_1M
    42. 

  42. #define MX53_ETB_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00001000)
    43. 

  43. #define MX53_ETM_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00002000)
    44. 

  44. #define MX53_TPIU_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00003000)
    45. 

  45. #define MX53_CTI0_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00004000)
    46. 

  46. #define MX53_CTI1_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00005000)
    47. 

  47. #define MX53_CTI2_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00006000)
    48. 

  48. #define MX53_CTI3_BASE_ADDR		(MX53_DEBUG_BASE_ADDR + 0x00007000)
    49. 

  49. #define MX53_CORTEX_DBG_BASE_ADDR	(MX53_DEBUG_BASE_ADDR + 0x00008000)
    50. 

  50. 

  51. /*
    52. 

  52.  * SPBA global module enabled #0
    53. 

  53.  */
    54. 

  54. #define MX53_SPBA0_BASE_ADDR		0x50000000
    55. 

  55. #define MX53_SPBA0_SIZE		SZ_1M
    56. 

  56. 

  57. #define MX53_ESDHC1_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00004000)
    58. 

  58. #define MX53_ESDHC2_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00008000)
    59. 

  59. #define MX53_UART3_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0000C000)
    60. 

  60. #define MX53_ECSPI1_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00010000)
    61. 

  61. #define MX53_SSI2_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00014000)
    62. 

  62. #define MX53_ESDHC3_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00020000)
    63. 

  63. #define MX53_ESDHC4_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00024000)
    64. 

  64. #define MX53_SPDIF_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00028000)
    65. 

  65. #define MX53_ASRC_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0002C000)
    66. 

  66. #define MX53_ATA_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00030000)
    67. 

  67. #define MX53_SLIM_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00034000)
    68. 

  68. #define MX53_HSI2C_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00038000)
    69. 

  69. #define MX53_SPBA_CTRL_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x0003C000)
    70. 

  70. 

  71. /*
    72. 

  72.  * AIPS 1
    73. 

  73.  */
    74. 

  74. #define MX53_AIPS1_BASE_ADDR	0x53F00000
    75. 

  75. #define MX53_AIPS1_SIZE		SZ_1M
    76. 

  76. 

  77. #define MX53_OTG_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00080000)
    78. 

  78. #define MX53_GPIO1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00084000)
    79. 

  79. #define MX53_GPIO2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00088000)
    80. 

  80. #define MX53_GPIO3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0008C000)
    81. 

  81. #define MX53_GPIO4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00090000)
    82. 

  82. #define MX53_KPP_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00094000)
    83. 

  83. #define MX53_WDOG1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00098000)
    84. 

  84. #define MX53_WDOG2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0009C000)
    85. 

  85. #define MX53_GPT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A0000)
    86. 

  86. #define MX53_SRTC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A4000)
    87. 

  87. #define MX53_IOMUXC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A8000)
    88. 

  88. #define MX53_EPIT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000AC000)
    89. 

  89. #define MX53_EPIT2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B0000)
    90. 

  90. #define MX53_PWM1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B4000)
    91. 

  91. #define MX53_PWM2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B8000)
    92. 

  92. #define MX53_UART1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000BC000)
    93. 

  93. #define MX53_UART2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000C0000)
    94. 

  94. #define MX53_SRC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D0000)
    95. 

  95. #define MX53_CCM_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D4000)
    96. 

  96. #define MX53_GPC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D8000)
    97. 

  97. #define MX53_GPIO5_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000DC000)
    98. 

  98. #define MX53_GPIO6_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E0000)
    99. 

  99. #define MX53_GPIO7_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E4000)
    100. 

  100. #define MX53_ATA_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E8000)
    101. 

  101. #define MX53_I2C3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000EC000)
    102. 

  102. #define MX53_UART4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000F0000)
    103. 

  103. 

  104. /*
    105. 

  105.  * AIPS 2
    106. 

  106.  */
    107. 

  107. #define MX53_AIPS2_BASE_ADDR		0x63F00000
    108. 

  108. #define MX53_AIPS2_SIZE			SZ_1M
    109. 

  109. 

  110. #define MX53_PLL1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00080000)
    111. 

  111. #define MX53_PLL2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00084000)
    112. 

  112. #define MX53_PLL3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00088000)
    113. 

  113. #define MX53_PLL4_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0008C000)
    114. 

  114. #define MX53_UART5_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00090000)
    115. 

  115. #define MX53_AHBMAX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00094000)
    116. 

  116. #define MX53_IIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00098000)
    117. 

  117. #define MX53_CSU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0009C000)
    118. 

  118. #define MX53_ARM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A0000)
    119. 

  119. #define MX53_OWIRE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A4000)
    120. 

  120. #define MX53_FIRI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A8000)
    121. 

  121. #define MX53_ECSPI2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000AC000)
    122. 

  122. #define MX53_SDMA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B0000)
    123. 

  123. #define MX53_SCC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B4000)
    124. 

  124. #define MX53_ROMCP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B8000)
    125. 

  125. #define MX53_RTIC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000BC000)
    126. 

  126. #define MX53_CSPI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C0000)
    127. 

  127. #define MX53_I2C2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C4000)
    128. 

  128. #define MX53_I2C1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C8000)
    129. 

  129. #define MX53_SSI1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000CC000)
    130. 

  130. #define MX53_AUDMUX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D0000)
    131. 

  131. #define MX53_RTC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D4000)
    132. 

  132. #define MX53_M4IF_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D8000)
    133. 

  133. #define MX53_ESDCTL_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D9000)
    134. 

  134. #define MX53_WEIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DA000)
    135. 

  135. #define MX53_NFC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DB000)
    136. 

  136. #define MX53_EMI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DBF00)
    137. 

  137. #define MX53_MIPI_HSC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DC000)
    138. 

  138. #define MX53_MLB_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E4000)
    139. 

  139. #define MX53_SSI3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E8000)
    140. 

  140. #define MX53_FEC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000EC000)
    141. 

  141. #define MX53_TVE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F0000)
    142. 

  142. #define MX53_VPU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F4000)
    143. 

  143. #define MX53_SAHARA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F8000)
    144. 

  144. #define MX53_PTP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000FC000)
    145. 

  145. 

  146. /*
    147. 

  147.  * Memory regions and CS
    148. 

  148.  */
    149. 

  149. #define MX53_CSD0_BASE_ADDR		0x70000000
    150. 

  150. #define MX53_CSD1_BASE_ADDR		0xB0000000
    151. 

  151. #define MX53_CS0_BASE_ADDR		0xF0000000
    152. 

  152. #define MX53_CS1_32MB_BASE_ADDR	0xF2000000
    153. 

  153. #define MX53_CS1_64MB_BASE_ADDR		0xF4000000
    154. 

  154. #define MX53_CS2_64MB_BASE_ADDR		0xF4000000
    155. 

  155. #define MX53_CS2_96MB_BASE_ADDR		0xF6000000
    156. 

  156. #define MX53_CS3_BASE_ADDR		0xF6000000
    157. 

  157. 

  158. #define MX53_IO_P2V(x)			IMX_IO_P2V(x)
    159. 

  159. #define MX53_IO_ADDRESS(x)		IOMEM(MX53_IO_P2V(x))
    160. 

  160. 

  161. /*
    162. 

  162.  * defines for SPBA modules
    163. 

  163.  */
    164. 

  164. #define MX53_SPBA_SDHC1	0x04
    165. 

  165. #define MX53_SPBA_SDHC2	0x08
    166. 

  166. #define MX53_SPBA_UART3	0x0C
    167. 

  167. #define MX53_SPBA_CSPI1	0x10
    168. 

  168. #define MX53_SPBA_SSI2		0x14
    169. 

  169. #define MX53_SPBA_SDHC3	0x20
    170. 

  170. #define MX53_SPBA_SDHC4	0x24
    171. 

  171. #define MX53_SPBA_SPDIF	0x28
    172. 

  172. #define MX53_SPBA_ATA		0x30
    173. 

  173. #define MX53_SPBA_SLIM		0x34
    174. 

  174. #define MX53_SPBA_HSI2C	0x38
    175. 

  175. #define MX53_SPBA_CTRL		0x3C
    176. 

  176. 

  177. /*
    178. 

  178.  * DMA request assignments
    179. 

  179.  */
    180. 

  180. #define MX53_DMA_REQ_SSI3_TX0		47
    181.