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synchronousMemoryDatabase.h

synchronousMemoryDatabase.h 6.0 KB
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  1. #ifndef __MACH_MX50_H__
    2. 

  2. #define __MACH_MX50_H__
    3. 

  3. 

  4. /*
    5. 

  5.  * IROM
    6. 

  6.  */
    7. 

  7. #define MX50_IROM_BASE_ADDR		0x0
    8. 

  8. #define MX50_IROM_SIZE			SZ_64K
    9. 

  9. 

  10. /* TZIC */
    11. 

  11. #define MX50_TZIC_BASE_ADDR		0x0fffc000
    12. 

  12. #define MX50_TZIC_SIZE			SZ_16K
    13. 

  13. 

  14. /*
    15. 

  15.  * IRAM
    16. 

  16.  */
    17. 

  17. #define MX50_IRAM_BASE_ADDR	0xf8000000	/* internal ram */
    18. 

  18. #define MX50_IRAM_PARTITIONS	16
    19. 

  19. #define MX50_IRAM_SIZE		(MX50_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
    20. 

  20. 

  21. /*
    22. 

  22.  * Databahn
    23. 

  23.  */
    24. 

  24. #define MX50_DATABAHN_BASE_ADDR			0x14000000
    25. 

  25. 

  26. /*
    27. 

  27.  * Graphics Memory of GPU
    28. 

  28.  */
    29. 

  29. #define MX50_GPU2D_BASE_ADDR		0x20000000
    30. 

  30. 

  31. #define MX50_DEBUG_BASE_ADDR		0x40000000
    32. 

  32. #define MX50_DEBUG_SIZE			SZ_1M
    33. 

  33. #define MX50_ETB_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00001000)
    34. 

  34. #define MX50_ETM_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00002000)
    35. 

  35. #define MX50_TPIU_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00003000)
    36. 

  36. #define MX50_CTI0_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00004000)
    37. 

  37. #define MX50_CTI1_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00005000)
    38. 

  38. #define MX50_CTI2_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00006000)
    39. 

  39. #define MX50_CTI3_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x00007000)
    40. 

  40. #define MX50_CORTEX_DBG_BASE_ADDR	(MX50_DEBUG_BASE_ADDR + 0x00008000)
    41. 

  41. 

  42. #define MX50_APBHDMA_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01000000)
    43. 

  43. #define MX50_OCOTP_CTRL_BASE_ADDR	(MX50_DEBUG_BASE_ADDR + 0x01002000)
    44. 

  44. #define MX50_DIGCTL_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01004000)
    45. 

  45. #define MX50_GPMI_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01006000)
    46. 

  46. #define MX50_BCH_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01008000)
    47. 

  47. #define MX50_ELCDIF_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x0100a000)
    48. 

  48. #define MX50_EPXP_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x0100c000)
    49. 

  49. #define MX50_DCP_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x0100e000)
    50. 

  50. #define MX50_EPDC_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01010000)
    51. 

  51. #define MX50_QOSC_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01012000)
    52. 

  52. #define MX50_PERFMON_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01014000)
    53. 

  53. #define MX50_SSP_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01016000)
    54. 

  54. #define MX50_ANATOP_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x01018000)
    55. 

  55. #define MX50_NIC_BASE_ADDR		(MX50_DEBUG_BASE_ADDR + 0x08000000)
    56. 

  56. 

  57. /*
    58. 

  58.  * SPBA global module enabled #0
    59. 

  59.  */
    60. 

  60. #define MX50_SPBA0_BASE_ADDR		0x50000000
    61. 

  61. #define MX50_SPBA0_SIZE			SZ_1M
    62. 

  62. 

  63. #define MX50_MMC_SDHC1_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00004000)
    64. 

  64. #define MX50_MMC_SDHC2_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00008000)
    65. 

  65. #define MX50_UART3_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x0000c000)
    66. 

  66. #define MX50_CSPI1_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x00010000)
    67. 

  67. #define MX50_SSI2_BASE_ADDR		(MX50_SPBA0_BASE_ADDR + 0x00014000)
    68. 

  68. #define MX50_MMC_SDHC3_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00020000)
    69. 

  69. #define MX50_MMC_SDHC4_BASE_ADDR	(MX50_SPBA0_BASE_ADDR + 0x00024000)
    70. 

  70. 

  71. /*
    72. 

  72.  * AIPS 1
    73. 

  73.  */
    74. 

  74. #define MX50_AIPS1_BASE_ADDR	0x53f00000
    75. 

  75. #define MX50_AIPS1_SIZE		SZ_1M
    76. 

  76. 

  77. #define MX50_OTG_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00080000)
    78. 

  78. #define MX50_GPIO1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00084000)
    79. 

  79. #define MX50_GPIO2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00088000)
    80. 

  80. #define MX50_GPIO3_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x0008c000)
    81. 

  81. #define MX50_GPIO4_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00090000)
    82. 

  82. #define MX50_KPP_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00094000)
    83. 

  83. #define MX50_WDOG_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x00098000)
    84. 

  84. #define MX50_GPT1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000a0000)
    85. 

  85. #define MX50_SRTC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000a4000)
    86. 

  86. #define MX50_IOMUXC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000a8000)
    87. 

  87. #define MX50_EPIT1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000ac000)
    88. 

  88. #define MX50_PWM1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000b4000)
    89. 

  89. #define MX50_PWM2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000b8000)
    90. 

  90. #define MX50_UART1_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000bc000)
    91. 

  91. #define MX50_UART2_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000c0000)
    92. 

  92. #define MX50_SRC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000d0000)
    93. 

  93. #define MX50_CCM_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000d4000)
    94. 

  94. #define MX50_GPC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000d8000)
    95. 

  95. #define MX50_GPIO5_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000dc000)
    96. 

  96. #define MX50_GPIO6_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000e0000)
    97. 

  97. #define MX50_I2C3_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000ec000)
    98. 

  98. #define MX50_UART4_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000f0000)
    99. 

  99. 

  100. #define MX50_MSHC_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000f4000)
    101. 

  101. #define MX50_RNGB_BASE_ADDR	(MX50_AIPS1_BASE_ADDR + 0x000f8000)
    102. 

  102. 

  103. /*
    104. 

  104.  * AIPS 2
    105. 

  105.  */
    106. 

  106. #define MX50_AIPS2_BASE_ADDR	0x63f00000
    107. 

  107. #define MX50_AIPS2_SIZE		SZ_1M
    108. 

  108. 

  109. #define MX50_PLL1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00080000)
    110. 

  110. #define MX50_PLL2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00084000)
    111. 

  111. #define MX50_PLL3_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00088000)
    112. 

  112. #define MX50_UART5_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00090000)
    113. 

  113. #define MX50_AHBMAX_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x00094000)
    114. 

  114. #define MX50_ARM_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000a0000)
    115. 

  115. #define MX50_OWIRE_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000a4000)
    116. 

  116. #define MX50_CSPI2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000ac000)
    117. 

  117. #define MX50_SDMA_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000b0000)
    118. 

  118. #define MX50_ROMCP_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000b8000)
    119. 

  119. #define MX50_CSPI3_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000c0000)
    120. 

  120. #define MX50_I2C2_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000c4000)
    121. 

  121. #define MX50_I2C1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000c8000)
    122. 

  122. #define MX50_SSI1_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000cc000)
    123. 

  123. #define MX50_AUDMUX_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000d0000)
    124. 

  124. #define MX50_WEIM_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000d8000)
    125. 

  125. #define MX50_FEC_BASE_ADDR	(MX50_AIPS2_BASE_ADDR + 0x000ec000)
    126. 

  126. 

  127. /*
    128. 

  128.  * Memory regions and CS
    129. 

  129.  */
    130. 

  130. #define MX50_CSD0_BASE_ADDR		0x70000000
    131. 

  131. #define MX50_CSD1_BASE_ADDR		0xb0000000
    132. 

  132. #define MX50_CS0_BASE_ADDR		0xf0000000
    133. 

  133. 

  134. #define MX50_IO_P2V(x)			IMX_IO_P2V(x)
    135. 

  135. #define MX50_IO_ADDRESS(x)		IOMEM(MX50_IO_P2V(x))
    136. 

  136. 

  137. /*
    138. 

  138.  * defines for SPBA modules
    139. 

  139.  */
    140. 

  140. #define MX50_SPBA_SDHC1		0x04
    141. 

  141. #define MX50_SPBA_SDHC2		0x08
    142. 

  142. #define MX50_SPBA_UART3		0x0c
    143. 

  143. #define MX50_SPBA_CSPI1		0x10
    144. 

  144. #define MX50_SPBA_SSI2		0x14
    145. 

  145. #define MX50_SPBA_SDHC3		0x20
    146. 

  146. #define MX50_SPBA_SDHC4		0x24
    147. 

  147. #define MX50_SPBA_SPDIF		0x28
    148. 

  148. #define MX50_SPBA_ATA		0x30
    149. 

  149. #define MX50_SPBA_SLIM		0x34
    150. 

  150. #define MX50_SPBA_HSI2C		0x38
    151. 

  151. #define MX50_SPBA_CTRL		0x3c
    152. 

  152. 

  153. /*
    154. 

  154.  * DMA request assignments
    155. 

  155.  */
    156. 

  156. #define MX50_DMA_REQ_GPC		1
    157. 

  157. #define MX50_DMA_REQ_ATA_UART4_RX	2
    158.