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realizationOfDataCalculation.h

realizationOfDataCalculation.h 5.0 KB
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  1. /*
    2. 

  2.  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
    3. 

  3.  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
    4. 

  4.  *
    5. 

  5.  * This contains i.MX27-specific hardware definitions. For those
    6. 

  6.  * hardware pieces that are common between i.MX21 and i.MX27, have a
    7. 

  7.  * look at mx2x.h.
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or
    10. 

  10.  * modify it under the terms of the GNU General Public License
    11. 

  11.  * as published by the Free Software Foundation; either version 2
    12. 

  12.  * of the License, or (at your option) any later version.
    13. 

  13.  * This program is distributed in the hope that it will be useful,
    14. 

  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16. 

  16.  * GNU General Public License for more details.
    17. 

  17.  *
    18. 

  18.  * You should have received a copy of the GNU General Public License
    19. 

  19.  * along with this program; if not, write to the Free Software
    20. 

  20.  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
    21. 

  21.  * MA  02110-1301, USA.
    22. 

  22.  */
    23. 

  23. 

  24. #ifndef __MACH_MX27_H__
    25. 

  25. #define __MACH_MX27_H__
    26. 

  26. 

  27. #define MX27_AIPI_BASE_ADDR		0x10000000
    28. 

  28. #define MX27_AIPI_SIZE			SZ_1M
    29. 

  29. #define MX27_DMA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x01000)
    30. 

  30. #define MX27_WDOG_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x02000)
    31. 

  31. #define MX27_GPT1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x03000)
    32. 

  32. #define MX27_GPT2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x04000)
    33. 

  33. #define MX27_GPT3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x05000)
    34. 

  34. #define MX27_PWM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x06000)
    35. 

  35. #define MX27_RTC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x07000)
    36. 

  36. #define MX27_KPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x08000)
    37. 

  37. #define MX27_OWIRE_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x09000)
    38. 

  38. #define MX27_UART1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0a000)
    39. 

  39. #define MX27_UART2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0b000)
    40. 

  40. #define MX27_UART3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0c000)
    41. 

  41. #define MX27_UART4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0d000)
    42. 

  42. #define MX27_CSPI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0e000)
    43. 

  43. #define MX27_CSPI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0f000)
    44. 

  44. #define MX27_SSI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x10000)
    45. 

  45. #define MX27_SSI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x11000)
    46. 

  46. #define MX27_I2C1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x12000)
    47. 

  47. #define MX27_SDHC1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x13000)
    48. 

  48. #define MX27_SDHC2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x14000)
    49. 

  49. #define MX27_GPIO_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x15000)
    50. 

  50. #define MX27_GPIO1_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x000)
    51. 

  51. #define MX27_GPIO2_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x100)
    52. 

  52. #define MX27_GPIO3_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x200)
    53. 

  53. #define MX27_GPIO4_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x300)
    54. 

  54. #define MX27_GPIO5_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x400)
    55. 

  55. #define MX27_GPIO6_BASE_ADDR			(MX27_GPIO_BASE_ADDR + 0x500)
    56. 

  56. #define MX27_AUDMUX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x16000)
    57. 

  57. #define MX27_CSPI3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x17000)
    58. 

  58. #define MX27_MSHC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x18000)
    59. 

  59. #define MX27_GPT4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x19000)
    60. 

  60. #define MX27_GPT5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1a000)
    61. 

  61. #define MX27_UART5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1b000)
    62. 

  62. #define MX27_UART6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1c000)
    63. 

  63. #define MX27_I2C2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1d000)
    64. 

  64. #define MX27_SDHC3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1e000)
    65. 

  65. #define MX27_GPT6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1f000)
    66. 

  66. #define MX27_LCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x21000)
    67. 

  67. #define MX27_SLCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x22000)
    68. 

  68. #define MX27_VPU_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x23000)
    69. 

  69. #define MX27_USB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x24000)
    70. 

  70. #define MX27_USB_OTG_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0000)
    71. 

  71. #define MX27_USB_HS1_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0200)
    72. 

  72. #define MX27_USB_HS2_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0400)
    73. 

  73. #define MX27_SAHARA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x25000)
    74. 

  74. #define MX27_EMMAPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26000)
    75. 

  75. #define MX27_EMMAPRP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26400)
    76. 

  76. #define MX27_CCM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27000)
    77. 

  77. #define MX27_SYSCTRL_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27800)
    78. 

  78. #define MX27_IIM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x28000)
    79. 

  79. #define MX27_RTIC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2a000)
    80. 

  80. #define MX27_FEC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2b000)
    81. 

  81. #define MX27_SCC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2c000)
    82. 

  82. #define MX27_ETB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3b000)
    83. 

  83. #define MX27_ETB_RAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3c000)
    84. 

  84. #define MX27_JAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3e000)
    85. 

  85. #define MX27_MAX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3f000)
    86. 

  86. 

  87. #define MX27_AVIC_BASE_ADDR		0x10040000
    88. 

  88. 

  89. /* ROM patch */
    90. 

  90. #define MX27_ROMP_BASE_ADDR		0x10041000
    91. 

  91. 

  92. #define MX27_SAHB1_BASE_ADDR		0x80000000
    93. 

  93. #define MX27_SAHB1_SIZE			SZ_1M
    94. 

  94. #define MX27_CSI_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x0000)
    95. 

  95. #define MX27_ATA_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x1000)
    96. 

  96. 

  97. /* Memory regions and CS */
    98. 

  98. #define MX27_SDRAM_BASE_ADDR		0xa0000000
    99. 

  99. #define MX27_CSD1_BASE_ADDR		0xb0000000
    100.