hiddenDangerAnalysis.c 14 KB

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  1. /*
  2. * Support for the Arcom ZEUS.
  3. *
  4. * Copyright (C) 2006 Arcom Control Systems Ltd.
  5. *
  6. * Loosely based on Arcom's 2.6.16.28.
  7. * Maintained by Marc Zyngier <maz@misterjones.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/cpufreq.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/pm.h>
  17. #include <linux/gpio.h>
  18. #include <linux/serial_8250.h>
  19. #include <linux/dm9000.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/pxa2xx_spi.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <linux/i2c.h>
  27. #include <linux/i2c/pxa-i2c.h>
  28. #include <linux/i2c/pca953x.h>
  29. #include <linux/apm-emulation.h>
  30. #include <linux/can/platform/mcp251x.h>
  31. #include <asm/mach-types.h>
  32. #include <asm/suspend.h>
  33. #include <asm/system_info.h>
  34. #include <asm/mach/arch.h>
  35. #include <asm/mach/map.h>
  36. #include <mach/pxa27x.h>
  37. #include <mach/regs-uart.h>
  38. #include <linux/platform_data/usb-ohci-pxa27x.h>
  39. #include <linux/platform_data/mmc-pxamci.h>
  40. #include <mach/pxa27x-udc.h>
  41. #include <mach/udc.h>
  42. #include <linux/platform_data/video-pxafb.h>
  43. #include <mach/pm.h>
  44. #include <mach/audio.h>
  45. #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
  46. #include <mach/zeus.h>
  47. #include <mach/smemc.h>
  48. #include "generic.h"
  49. /*
  50. * Interrupt handling
  51. */
  52. static unsigned long zeus_irq_enabled_mask;
  53. static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  54. static const int zeus_isa_irq_map[] = {
  55. 0, /* ISA irq #0, invalid */
  56. 0, /* ISA irq #1, invalid */
  57. 0, /* ISA irq #2, invalid */
  58. 1 << 0, /* ISA irq #3 */
  59. 1 << 1, /* ISA irq #4 */
  60. 1 << 2, /* ISA irq #5 */
  61. 1 << 3, /* ISA irq #6 */
  62. 1 << 4, /* ISA irq #7 */
  63. 0, /* ISA irq #8, invalid */
  64. 0, /* ISA irq #9, invalid */
  65. 1 << 5, /* ISA irq #10 */
  66. 1 << 6, /* ISA irq #11 */
  67. 1 << 7, /* ISA irq #12 */
  68. };
  69. static inline int zeus_irq_to_bitmask(unsigned int irq)
  70. {
  71. return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  72. }
  73. static inline int zeus_bit_to_irq(int bit)
  74. {
  75. return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  76. }
  77. static void zeus_ack_irq(struct irq_data *d)
  78. {
  79. __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  80. }
  81. static void zeus_mask_irq(struct irq_data *d)
  82. {
  83. zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  84. }
  85. static void zeus_unmask_irq(struct irq_data *d)
  86. {
  87. zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
  88. }
  89. static inline unsigned long zeus_irq_pending(void)
  90. {
  91. return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
  92. }
  93. static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
  94. {
  95. unsigned long pending;
  96. pending = zeus_irq_pending();
  97. do {
  98. /* we're in a chained irq handler,
  99. * so ack the interrupt by hand */
  100. desc->irq_data.chip->irq_ack(&desc->irq_data);
  101. if (likely(pending)) {
  102. irq = zeus_bit_to_irq(__ffs(pending));
  103. generic_handle_irq(irq);
  104. }
  105. pending = zeus_irq_pending();
  106. } while (pending);
  107. }
  108. static struct irq_chip zeus_irq_chip = {
  109. .name = "ISA",
  110. .irq_ack = zeus_ack_irq,
  111. .irq_mask = zeus_mask_irq,
  112. .irq_unmask = zeus_unmask_irq,
  113. };
  114. static void __init zeus_init_irq(void)
  115. {
  116. int level;
  117. int isa_irq;
  118. pxa27x_init_irq();
  119. /* Peripheral IRQs. It would be nice to move those inside driver
  120. configuration, but it is not supported at the moment. */
  121. irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
  122. irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
  123. irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
  124. irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
  125. IRQ_TYPE_EDGE_FALLING);
  126. irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
  127. /* Setup ISA IRQs */
  128. for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
  129. isa_irq = zeus_bit_to_irq(level);
  130. irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
  131. handle_edge_irq);
  132. set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
  133. }
  134. irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
  135. irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
  136. }
  137. /*
  138. * Platform devices
  139. */
  140. /* Flash */
  141. static struct resource zeus_mtd_resources[] = {
  142. [0] = { /* NOR Flash (up to 64MB) */
  143. .start = ZEUS_FLASH_PHYS,
  144. .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
  145. .flags = IORESOURCE_MEM,
  146. },
  147. [1] = { /* SRAM */
  148. .start = ZEUS_SRAM_PHYS,
  149. .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
  150. .flags = IORESOURCE_MEM,
  151. },
  152. };
  153. static struct physmap_flash_data zeus_flash_data[] = {
  154. [0] = {
  155. .width = 2,
  156. .parts = NULL,
  157. .nr_parts = 0,
  158. },
  159. };
  160. static struct platform_device zeus_mtd_devices[] = {
  161. [0] = {
  162. .name = "physmap-flash",
  163. .id = 0,
  164. .dev = {
  165. .platform_data = &zeus_flash_data[0],
  166. },
  167. .resource = &zeus_mtd_resources[0],
  168. .num_resources = 1,
  169. },
  170. };
  171. /* Serial */
  172. static struct resource zeus_serial_resources[] = {
  173. {
  174. .start = 0x10000000,
  175. .end = 0x1000000f,
  176. .flags = IORESOURCE_MEM,
  177. },
  178. {
  179. .start = 0x10800000,
  180. .end = 0x1080000f,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. {
  184. .start = 0x11000000,
  185. .end = 0x1100000f,
  186. .flags = IORESOURCE_MEM,
  187. },
  188. {
  189. .start = 0x40100000,
  190. .end = 0x4010001f,
  191. .flags = IORESOURCE_MEM,
  192. },
  193. {
  194. .start = 0x40200000,
  195. .end = 0x4020001f,
  196. .flags = IORESOURCE_MEM,
  197. },
  198. {
  199. .start = 0x40700000,
  200. .end = 0x4070001f,
  201. .flags = IORESOURCE_MEM,
  202. },
  203. };
  204. static struct plat_serial8250_port serial_platform_data[] = {
  205. /* External UARTs */
  206. /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
  207. { /* COM1 */
  208. .mapbase = 0x10000000,
  209. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
  210. .irqflags = IRQF_TRIGGER_RISING,
  211. .uartclk = 14745600,
  212. .regshift = 1,
  213. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  214. .iotype = UPIO_MEM,
  215. },
  216. { /* COM2 */
  217. .mapbase = 0x10800000,
  218. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
  219. .irqflags = IRQF_TRIGGER_RISING,
  220. .uartclk = 14745600,
  221. .regshift = 1,
  222. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  223. .iotype = UPIO_MEM,
  224. },
  225. { /* COM3 */
  226. .mapbase = 0x11000000,
  227. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
  228. .irqflags = IRQF_TRIGGER_RISING,
  229. .uartclk = 14745600,
  230. .regshift = 1,
  231. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  232. .iotype = UPIO_MEM,
  233. },
  234. { /* COM4 */
  235. .mapbase = 0x11800000,
  236. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
  237. .irqflags = IRQF_TRIGGER_RISING,
  238. .uartclk = 14745600,
  239. .regshift = 1,
  240. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  241. .iotype = UPIO_MEM,
  242. },
  243. /* Internal UARTs */
  244. { /* FFUART */
  245. .membase = (void *)&FFUART,
  246. .mapbase = __PREG(FFUART),
  247. .irq = IRQ_FFUART,
  248. .uartclk = 921600 * 16,
  249. .regshift = 2,
  250. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  251. .iotype = UPIO_MEM,
  252. },
  253. { /* BTUART */
  254. .membase = (void *)&BTUART,
  255. .mapbase = __PREG(BTUART),
  256. .irq = IRQ_BTUART,
  257. .uartclk = 921600 * 16,
  258. .regshift = 2,
  259. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  260. .iotype = UPIO_MEM,
  261. },
  262. { /* STUART */
  263. .membase = (void *)&STUART,
  264. .mapbase = __PREG(STUART),
  265. .irq = IRQ_STUART,
  266. .uartclk = 921600 * 16,
  267. .regshift = 2,
  268. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  269. .iotype = UPIO_MEM,
  270. },
  271. { },
  272. };
  273. static struct platform_device zeus_serial_device = {
  274. .name = "serial8250",
  275. .id = PLAT8250_DEV_PLATFORM,
  276. .dev = {
  277. .platform_data = serial_platform_data,
  278. },
  279. .num_resources = ARRAY_SIZE(zeus_serial_resources),
  280. .resource = zeus_serial_resources,
  281. };
  282. /* Ethernet */
  283. static struct resource zeus_dm9k0_resource[] = {
  284. [0] = {
  285. .start = ZEUS_ETH0_PHYS,
  286. .end = ZEUS_ETH0_PHYS + 1,
  287. .flags = IORESOURCE_MEM
  288. },
  289. [1] = {
  290. .start = ZEUS_ETH0_PHYS + 2,
  291. .end = ZEUS_ETH0_PHYS + 3,
  292. .flags = IORESOURCE_MEM
  293. },
  294. [2] = {
  295. .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
  296. .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
  297. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  298. },
  299. };
  300. static struct resource zeus_dm9k1_resource[] = {
  301. [0] = {
  302. .start = ZEUS_ETH1_PHYS,
  303. .end = ZEUS_ETH1_PHYS + 1,
  304. .flags = IORESOURCE_MEM
  305. },
  306. [1] = {
  307. .start = ZEUS_ETH1_PHYS + 2,
  308. .end = ZEUS_ETH1_PHYS + 3,
  309. .flags = IORESOURCE_MEM,
  310. },
  311. [2] = {
  312. .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
  313. .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
  314. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  315. },
  316. };
  317. static struct dm9000_plat_data zeus_dm9k_platdata = {
  318. .flags = DM9000_PLATF_16BITONLY,
  319. };
  320. static struct platform_device zeus_dm9k0_device = {
  321. .name = "dm9000",
  322. .id = 0,
  323. .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
  324. .resource = zeus_dm9k0_resource,
  325. .dev = {
  326. .platform_data = &zeus_dm9k_platdata,
  327. }
  328. };
  329. static struct platform_device zeus_dm9k1_device = {
  330. .name = "dm9000",
  331. .id = 1,
  332. .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
  333. .resource = zeus_dm9k1_resource,
  334. .dev = {
  335. .platform_data = &zeus_dm9k_platdata,
  336. }
  337. };
  338. /* External SRAM */
  339. static struct resource zeus_sram_resource = {
  340. .start = ZEUS_SRAM_PHYS,
  341. .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
  342. .flags = IORESOURCE_MEM,
  343. };
  344. static struct platform_device zeus_sram_device = {
  345. .name = "pxa2xx-8bit-sram",
  346. .id = 0,
  347. .num_resources = 1,
  348. .resource = &zeus_sram_resource,
  349. };
  350. /* SPI interface on SSP3 */
  351. static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
  352. .num_chipselect = 1,
  353. .enable_dma = 1,
  354. };
  355. /* CAN bus on SPI */
  356. static int zeus_mcp2515_setup(struct spi_device *sdev)
  357. {
  358. int err;
  359. err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown");
  360. if (err)
  361. return err;
  362. err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1);
  363. if (err) {
  364. gpio_free(ZEUS_CAN_SHDN_GPIO);
  365. return err;
  366. }
  367. return 0;
  368. }
  369. static int zeus_mcp2515_transceiver_enable(int enable)
  370. {
  371. gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable);
  372. return 0;
  373. }
  374. static struct mcp251x_platform_data zeus_mcp2515_pdata = {
  375. .oscillator_frequency = 16*1000*1000,
  376. .board_specific_setup = zeus_mcp2515_setup,
  377. .power_enable = zeus_mcp2515_transceiver_enable,
  378. };
  379. static struct spi_board_info zeus_spi_board_info[] = {
  380. [0] = {
  381. .modalias = "mcp2515",
  382. .platform_data = &zeus_mcp2515_pdata,
  383. .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
  384. .max_speed_hz = 1*1000*1000,
  385. .bus_num = 3,
  386. .mode = SPI_MODE_0,
  387. .chip_select = 0,
  388. },
  389. };
  390. /* Leds */
  391. static struct gpio_led zeus_leds[] = {
  392. [0] = {
  393. .name = "zeus:yellow:1",
  394. .default_trigger = "heartbeat",
  395. .gpio = ZEUS_EXT0_GPIO(3),
  396. .active_low = 1,
  397. },
  398. [1] = {
  399. .name = "zeus:yellow:2",
  400. .default_trigger = "default-on",
  401. .gpio = ZEUS_EXT0_GPIO(4),
  402. .active_low = 1,
  403. },
  404. [2] = {
  405. .name = "zeus:yellow:3",
  406. .default_trigger = "default-on",
  407. .gpio = ZEUS_EXT0_GPIO(5),
  408. .active_low = 1,
  409. },
  410. };
  411. static struct gpio_led_platform_data zeus_leds_info = {
  412. .leds = zeus_leds,
  413. .num_leds = ARRAY_SIZE(zeus_leds),
  414. };
  415. static struct platform_device zeus_leds_device = {
  416. .name = "leds-gpio",
  417. .id = -1,
  418. .dev = {
  419. .platform_data = &zeus_leds_info,
  420. },
  421. };
  422. static void zeus_cf_reset(int state)
  423. {
  424. u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
  425. if (state)
  426. cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
  427. else
  428. cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
  429. __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
  430. }
  431. static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
  432. .cd_gpio = ZEUS_CF_CD_GPIO,
  433. .rdy_gpio = ZEUS_CF_RDY_GPIO,
  434. .pwr_gpio = ZEUS_CF_PWEN_GPIO,
  435. .reset = zeus_cf_reset,
  436. };
  437. static struct platform_device zeus_pcmcia_device = {
  438. .name = "zeus-pcmcia",
  439. .id = -1,
  440. .dev = {
  441. .platform_data = &zeus_pcmcia_info,
  442. },
  443. };
  444. static struct resource zeus_max6369_resource = {
  445. .start = ZEUS_CPLD_EXTWDOG_PHYS,
  446. .end = ZEUS_CPLD_EXTWDOG_PHYS,
  447. .flags = IORESOURCE_MEM,
  448. };
  449. struct platform_device zeus_max6369_device = {
  450. .name = "max6369_wdt",
  451. .id = -1,
  452. .resource = &zeus_max6369_resource,
  453. .num_resources = 1,
  454. };
  455. static struct platform_device *zeus_devices[] __initdata = {
  456. &zeus_serial_device,
  457. &zeus_mtd_devices[0],
  458. &zeus_dm9k0_device,
  459. &zeus_dm9k1_device,
  460. &zeus_sram_device,
  461. &zeus_leds_device,
  462. &zeus_pcmcia_device,
  463. &zeus_max6369_device,
  464. };
  465. /* AC'97 */
  466. static pxa2xx_audio_ops_t zeus_ac97_info = {
  467. .reset_gpio = 95,
  468. };
  469. /*
  470. * USB host
  471. */
  472. static int zeus_ohci_init(struct device *dev)
  473. {
  474. int err;
  475. /* Switch on port 2. */
  476. if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
  477. dev_err(dev, "Can't request USB2_PWREN\n");
  478. return err;
  479. }
  480. if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
  481. gpio_free(ZEUS_USB2_PWREN_GPIO);
  482. dev_err(dev, "Can't enable USB2_PWREN\n");
  483. return err;
  484. }
  485. /* Port 2 is shared between host and client interface. */
  486. UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
  487. return 0;
  488. }
  489. static void zeus_ohci_exit(struct device *dev)
  490. {
  491. /* Power-off port 2 */
  492. gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
  493. gpio_free(ZEUS_USB2_PWREN_GPIO);
  494. }
  495. static struct pxaohci_platform_data zeus_ohci_platform_data = {
  496. .port_mode = PMM_NPS_MODE,
  497. /* Clear Power Control Polarity Low and set Power Sense
  498. * Polarity Low. Supply power to USB ports. */
  499. .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
  500. .init = zeus_ohci_init,
  501. .exit = zeus_ohci_exit,
  502. };
  503. /*
  504. * Flat Panel
  505. */
  506. static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
  507. {
  508. gpio_set_value(ZEUS_LCD_EN_GPIO, on);
  509. }
  510. static void zeus_backlight_power(int on)
  511. {
  512. gpio_set_value(ZEUS_BKLEN_GPIO, on);
  513. }
  514. static int zeus_setup_fb_gpios(void)
  515. {
  516. int err;
  517. if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
  518. goto out_err;
  519. if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
  520. goto out_err_lcd;
  521. if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
  522. goto out_err_lcd;
  523. if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
  524. goto out_err_bkl;
  525. return 0;
  526. out_err_bkl:
  527. gpio_free(ZEUS_BKLEN_GPIO);
  528. out_err_lcd:
  529. gpio_free(ZEUS_LCD_EN_GPIO);
  530. out_err:
  531. return err;
  532. }
  533. static struct pxafb_mode_info zeus_fb_mode_info[] = {
  534. {
  535. .pixclock = 39722,
  536. .xres = 640,
  537. .yres = 480,
  538. .bpp = 16,
  539. .hsync_len = 63,
  540. .left_margin = 16,
  541. .right_margin = 81,
  542. .vsync_len = 2,
  543. .upper_margin = 12,
  544. .lower_margin = 31,
  545. .sync = 0,
  546. },
  547. };
  548. static struct pxafb_mach_info zeus_fb_info = {
  549. .modes = zeus_fb_mode_info,
  550. .num_modes = 1,
  551. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
  552. .pxafb_lcd_power = zeus_lcd_power,
  553. .pxafb_backlight_power = zeus_backlight_power,