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synchronousMemoryDatabase.h

synchronousMemoryDatabase.h 5.2 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *	m525xsim.h -- ColdFire 525x System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *	(C) Copyright 2012, Steven king <sfking@fdwdc.com>
    7. 

  7.  *	(C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
    8. 

  8.  */
    9. 

  9. 

  10. /****************************************************************************/
    11. 

  11. #ifndef	m525xsim_h
    12. 

  12. #define m525xsim_h
    13. 

  13. /****************************************************************************/
    14. 

  14. 

  15. /*
    16. 

  16.  *	This header supports ColdFire 5249, 5251 and 5253. There are a few
    17. 

  17.  *	little differences between them, but most of the peripheral support
    18. 

  18.  *	can be used by all of them.
    19. 

  19.  */
    20. 

  20. #define CPU_NAME		"COLDFIRE(m525x)"
    21. 

  21. #define CPU_INSTR_PER_JIFFY	3
    22. 

  22. #define MCF_BUSCLK		(MCF_CLK / 2)
    23. 

  23. 

  24. #include <asm/m52xxacr.h>
    25. 

  25. 

  26. /*
    27. 

  27.  *	The 525x has a second MBAR region, define its address.
    28. 

  28.  */
    29. 

  29. #define MCF_MBAR2		0x80000000
    30. 

  30. 

  31. /*
    32. 

  32.  *	Define the 525x SIM register set addresses.
    33. 

  33.  */
    34. 

  34. #define MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
    35. 

  35. #define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
    36. 

  36. #define MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
    37. 

  37. #define MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */
    38. 

  38. #define MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
    39. 

  39. #define MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
    40. 

  40. #define MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
    41. 

  41. #define MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
    42. 

  42. #define MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
    43. 

  43. #define MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
    44. 

  44. #define MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
    45. 

  45. #define MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
    46. 

  46. #define MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
    47. 

  47. #define MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
    48. 

  48. #define MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
    49. 

  49. #define MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
    50. 

  50. #define MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
    51. 

  51. #define MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
    52. 

  52. #define MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */
    53. 

  53. 

  54. #define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
    55. 

  55. #define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
    56. 

  56. #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
    57. 

  57. #define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
    58. 

  58. #define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
    59. 

  59. #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
    60. 

  60. #define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
    61. 

  61. #define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
    62. 

  62. #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
    63. 

  63. #define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
    64. 

  64. #define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
    65. 

  65. #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
    66. 

  66. #define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
    67. 

  67. #define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
    68. 

  68. #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
    69. 

  69. 

  70. #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
    71. 

  71. #define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
    72. 

  72. #define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
    73. 

  73. #define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
    74. 

  74. #define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
    75. 

  75. 

  76. /*
    77. 

  77.  * Secondary Interrupt Controller (in MBAR2)
    78. 

  78. */
    79. 

  79. #define MCFINTC2_INTBASE	(MCF_MBAR2 + 0x168)	/* Base Vector Reg */
    80. 

  80. #define MCFINTC2_INTPRI1	(MCF_MBAR2 + 0x140)	/* 0-7 priority */
    81. 

  81. #define MCFINTC2_INTPRI2	(MCF_MBAR2 + 0x144)	/* 8-15 priority */
    82. 

  82. #define MCFINTC2_INTPRI3	(MCF_MBAR2 + 0x148)	/* 16-23 priority */
    83. 

  83. #define MCFINTC2_INTPRI4	(MCF_MBAR2 + 0x14c)	/* 24-31 priority */
    84. 

  84. #define MCFINTC2_INTPRI5	(MCF_MBAR2 + 0x150)	/* 32-39 priority */
    85. 

  85. #define MCFINTC2_INTPRI6	(MCF_MBAR2 + 0x154)	/* 40-47 priority */
    86. 

  86. #define MCFINTC2_INTPRI7	(MCF_MBAR2 + 0x158)	/* 48-55 priority */
    87. 

  87. #define MCFINTC2_INTPRI8	(MCF_MBAR2 + 0x15c)	/* 56-63 priority */
    88. 

  88. 

  89. #define MCFINTC2_INTPRI_REG(i)	(MCFINTC2_INTPRI1 + \
    90. 

  90. 				((((i) - MCFINTC2_VECBASE) / 8) * 4))
    91. 

  91. #define MCFINTC2_INTPRI_BITS(b, i)	((b) << (((i) % 8) * 4))
    92. 

  92. 

  93. /*
    94. 

  94.  *	Timer module.
    95. 

  95.  */
    96. 

  96. #define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
    97. 

  97. #define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
    98. 

  98. 

  99. /*
    100. 

  100.  *	UART module.
    101. 

  101.  */
    102. 

  102. #define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
    103. 

  103. #define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
    104. 

  104. 

  105. /*
    106. 

  106.  *	QSPI module.
    107. 

  107.  */
    108. 

  108. #define MCFQSPI_BASE		(MCF_MBAR + 0x300)	/* Base address QSPI */
    109. 

  109. #define MCFQSPI_SIZE		0x40			/* Register set size */
    110. 

  110. 

  111. #ifdef CONFIG_M5249
    112. 

  112. #define MCFQSPI_CS0		29
    113. 

  113. #define MCFQSPI_CS1		24
    114. 

  114. #define MCFQSPI_CS2		21
    115. 

  115. #define MCFQSPI_CS3		22
    116. 

  116. #else
    117. 

  117. #define MCFQSPI_CS0		15
    118. 

  118. #define MCFQSPI_CS1		16
    119. 

  119. #define MCFQSPI_CS2		24
    120. 

  120. #define MCFQSPI_CS3		28
    121. 

  121. #endif
    122. 

  122. 

  123. /*
    124. 

  124.  *	I2C module.
    125. 

  125.  */
    126. 

  126. #define MCFI2C_BASE0		(MCF_MBAR + 0x280)	/* Base addreess I2C0 */
    127. 

  127. #define MCFI2C_SIZE0		0x20			/* Register set size */
    128. 

  128. 

  129. #define MCFI2C_BASE1		(MCF_MBAR2 + 0x440)	/* Base addreess I2C1 */
    130. 

  130. #define MCFI2C_SIZE1		0x20			/* Register set size */
    131. 

  131. 

  132. /*
    133. 

  133.  *	DMA unit base addresses.
    134. 

  134.  */
    135. 

  135. #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
    136. 

  136. #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
    137. 

  137. #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
    138. 

  138. #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
    139. 

  139. 

  140. /*
    141.