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aiot
/
waterDataPreprocessing
/
dataSharedMemory
/
memoryCall.h

memoryCall.h 7.3 KB
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  1. /*
    2. 

  2.  * Copyright 2007-2009 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _BF548_IRQ_H_
    8. 

  8. #define _BF548_IRQ_H_
    9. 

  9. 

  10. #include <mach-common/irq.h>
    11. 

  11. 

  12. #define NR_PERI_INTS		(3 * 32)
    13. 

  13. 

  14. #define IRQ_PLL_WAKEUP		BFIN_IRQ(0)	/* PLL Wakeup Interrupt */
    15. 

  15. #define IRQ_DMAC0_ERROR		BFIN_IRQ(1)	/* DMAC0 Status Interrupt */
    16. 

  16. #define IRQ_EPPI0_ERROR		BFIN_IRQ(2)	/* EPPI0 Error Interrupt */
    17. 

  17. #define IRQ_SPORT0_ERROR	BFIN_IRQ(3)	/* SPORT0 Error Interrupt */
    18. 

  18. #define IRQ_SPORT1_ERROR	BFIN_IRQ(4)	/* SPORT1 Error Interrupt */
    19. 

  19. #define IRQ_SPI0_ERROR		BFIN_IRQ(5)	/* SPI0 Status(Error) Interrupt */
    20. 

  20. #define IRQ_UART0_ERROR		BFIN_IRQ(6)	/* UART0 Status(Error) Interrupt */
    21. 

  21. #define IRQ_RTC			BFIN_IRQ(7)	/* RTC Interrupt */
    22. 

  22. #define IRQ_EPPI0		BFIN_IRQ(8)	/* EPPI0 Interrupt (DMA12) */
    23. 

  23. #define IRQ_SPORT0_RX		BFIN_IRQ(9)	/* SPORT0 RX Interrupt (DMA0) */
    24. 

  24. #define IRQ_SPORT0_TX		BFIN_IRQ(10)	/* SPORT0 TX Interrupt (DMA1) */
    25. 

  25. #define IRQ_SPORT1_RX		BFIN_IRQ(11)	/* SPORT1 RX Interrupt (DMA2) */
    26. 

  26. #define IRQ_SPORT1_TX		BFIN_IRQ(12)	/* SPORT1 TX Interrupt (DMA3) */
    27. 

  27. #define IRQ_SPI0		BFIN_IRQ(13)	/* SPI0 Interrupt (DMA4) */
    28. 

  28. #define IRQ_UART0_RX		BFIN_IRQ(14)	/* UART0 RX Interrupt (DMA6) */
    29. 

  29. #define IRQ_UART0_TX		BFIN_IRQ(15)	/* UART0 TX Interrupt (DMA7) */
    30. 

  30. #define IRQ_TIMER8		BFIN_IRQ(16)	/* TIMER 8 Interrupt */
    31. 

  31. #define IRQ_TIMER9		BFIN_IRQ(17)	/* TIMER 9 Interrupt */
    32. 

  32. #define IRQ_TIMER10		BFIN_IRQ(18)	/* TIMER 10 Interrupt */
    33. 

  33. #define IRQ_PINT0		BFIN_IRQ(19)	/* PINT0 Interrupt */
    34. 

  34. #define IRQ_PINT1		BFIN_IRQ(20)	/* PINT1 Interrupt */
    35. 

  35. #define IRQ_MDMAS0		BFIN_IRQ(21)	/* MDMA Stream 0 Interrupt */
    36. 

  36. #define IRQ_MDMAS1		BFIN_IRQ(22)	/* MDMA Stream 1 Interrupt */
    37. 

  37. #define IRQ_WATCH		BFIN_IRQ(23)	/* Watchdog Interrupt */
    38. 

  38. #define IRQ_DMAC1_ERROR		BFIN_IRQ(24)	/* DMAC1 Status (Error) Interrupt */
    39. 

  39. #define IRQ_SPORT2_ERROR	BFIN_IRQ(25)	/* SPORT2 Error Interrupt */
    40. 

  40. #define IRQ_SPORT3_ERROR	BFIN_IRQ(26)	/* SPORT3 Error Interrupt */
    41. 

  41. #define IRQ_MXVR_DATA		BFIN_IRQ(27)	/* MXVR Data Interrupt */
    42. 

  42. #define IRQ_SPI1_ERROR		BFIN_IRQ(28)	/* SPI1 Status (Error) Interrupt */
    43. 

  43. #define IRQ_SPI2_ERROR		BFIN_IRQ(29)	/* SPI2 Status (Error) Interrupt */
    44. 

  44. #define IRQ_UART1_ERROR		BFIN_IRQ(30)	/* UART1 Status (Error) Interrupt */
    45. 

  45. #define IRQ_UART2_ERROR		BFIN_IRQ(31)	/* UART2 Status (Error) Interrupt */
    46. 

  46. #define IRQ_CAN0_ERROR		BFIN_IRQ(32)	/* CAN0 Status (Error) Interrupt */
    47. 

  47. #define IRQ_SPORT2_RX		BFIN_IRQ(33)	/* SPORT2 RX (DMA18) Interrupt */
    48. 

  48. #define IRQ_SPORT2_TX		BFIN_IRQ(34)	/* SPORT2 TX (DMA19) Interrupt */
    49. 

  49. #define IRQ_SPORT3_RX		BFIN_IRQ(35)	/* SPORT3 RX (DMA20) Interrupt */
    50. 

  50. #define IRQ_SPORT3_TX		BFIN_IRQ(36)	/* SPORT3 TX (DMA21) Interrupt */
    51. 

  51. #define IRQ_EPPI1		BFIN_IRQ(37)	/* EPP1 (DMA13) Interrupt */
    52. 

  52. #define IRQ_EPPI2		BFIN_IRQ(38)	/* EPP2 (DMA14) Interrupt */
    53. 

  53. #define IRQ_SPI1		BFIN_IRQ(39)	/* SPI1 (DMA5) Interrupt */
    54. 

  54. #define IRQ_SPI2		BFIN_IRQ(40)	/* SPI2 (DMA23) Interrupt */
    55. 

  55. #define IRQ_UART1_RX		BFIN_IRQ(41)	/* UART1 RX (DMA8) Interrupt */
    56. 

  56. #define IRQ_UART1_TX		BFIN_IRQ(42)	/* UART1 TX (DMA9) Interrupt */
    57. 

  57. #define IRQ_ATAPI_RX		BFIN_IRQ(43)	/* ATAPI RX (DMA10) Interrupt */
    58. 

  58. #define IRQ_ATAPI_TX		BFIN_IRQ(44)	/* ATAPI TX (DMA11) Interrupt */
    59. 

  59. #define IRQ_TWI0		BFIN_IRQ(45)	/* TWI0 Interrupt */
    60. 

  60. #define IRQ_TWI1		BFIN_IRQ(46)	/* TWI1 Interrupt */
    61. 

  61. #define IRQ_CAN0_RX		BFIN_IRQ(47)	/* CAN0 Receive Interrupt */
    62. 

  62. #define IRQ_CAN0_TX		BFIN_IRQ(48)	/* CAN0 Transmit Interrupt */
    63. 

  63. #define IRQ_MDMAS2		BFIN_IRQ(49)	/* MDMA Stream 2 Interrupt */
    64. 

  64. #define IRQ_MDMAS3		BFIN_IRQ(50)	/* MDMA Stream 3 Interrupt */
    65. 

  65. #define IRQ_MXVR_ERROR		BFIN_IRQ(51)	/* MXVR Status (Error) Interrupt */
    66. 

  66. #define IRQ_MXVR_MSG		BFIN_IRQ(52)	/* MXVR Message Interrupt */
    67. 

  67. #define IRQ_MXVR_PKT		BFIN_IRQ(53)	/* MXVR Packet Interrupt */
    68. 

  68. #define IRQ_EPPI1_ERROR		BFIN_IRQ(54)	/* EPPI1 Error Interrupt */
    69. 

  69. #define IRQ_EPPI2_ERROR		BFIN_IRQ(55)	/* EPPI2 Error Interrupt */
    70. 

  70. #define IRQ_UART3_ERROR		BFIN_IRQ(56)	/* UART3 Status (Error) Interrupt */
    71. 

  71. #define IRQ_HOST_ERROR		BFIN_IRQ(57)	/* HOST Status (Error) Interrupt */
    72. 

  72. #define IRQ_PIXC_ERROR		BFIN_IRQ(59)	/* PIXC Status (Error) Interrupt */
    73. 

  73. #define IRQ_NFC_ERROR		BFIN_IRQ(60)	/* NFC Error Interrupt */
    74. 

  74. #define IRQ_ATAPI_ERROR		BFIN_IRQ(61)	/* ATAPI Error Interrupt */
    75. 

  75. #define IRQ_CAN1_ERROR		BFIN_IRQ(62)	/* CAN1 Status (Error) Interrupt */
    76. 

  76. #define IRQ_HS_DMA_ERROR	BFIN_IRQ(63)	/* Handshake DMA Status Interrupt */
    77. 

  77. #define IRQ_PIXC_IN0		BFIN_IRQ(64)	/* PIXC IN0 (DMA15) Interrupt */
    78. 

  78. #define IRQ_PIXC_IN1		BFIN_IRQ(65)	/* PIXC IN1 (DMA16) Interrupt */
    79. 

  79. #define IRQ_PIXC_OUT		BFIN_IRQ(66)	/* PIXC OUT (DMA17) Interrupt */
    80. 

  80. #define IRQ_SDH			BFIN_IRQ(67)	/* SDH/NFC (DMA22) Interrupt */
    81. 

  81. #define IRQ_CNT			BFIN_IRQ(68)	/* CNT Interrupt */
    82. 

  82. #define IRQ_KEY			BFIN_IRQ(69)	/* KEY Interrupt */
    83. 

  83. #define IRQ_CAN1_RX		BFIN_IRQ(70)	/* CAN1 RX Interrupt */
    84. 

  84. #define IRQ_CAN1_TX		BFIN_IRQ(71)	/* CAN1 TX Interrupt */
    85. 

  85. #define IRQ_SDH_MASK0		BFIN_IRQ(72)	/* SDH Mask 0 Interrupt */
    86. 

  86. #define IRQ_SDH_MASK1		BFIN_IRQ(73)	/* SDH Mask 1 Interrupt */
    87. 

  87. #define IRQ_USB_INT0		BFIN_IRQ(75)	/* USB INT0 Interrupt */
    88. 

  88. #define IRQ_USB_INT1		BFIN_IRQ(76)	/* USB INT1 Interrupt */
    89. 

  89. #define IRQ_USB_INT2		BFIN_IRQ(77)	/* USB INT2 Interrupt */
    90. 

  90. #define IRQ_USB_DMA		BFIN_IRQ(78)	/* USB DMA Interrupt */
    91. 

  91. #define IRQ_OPTSEC		BFIN_IRQ(79)	/* OTPSEC Interrupt */
    92. 

  92. #define IRQ_TIMER0		BFIN_IRQ(86)	/* Timer 0 Interrupt */
    93. 

  93. #define IRQ_TIMER1		BFIN_IRQ(87)	/* Timer 1 Interrupt */
    94. 

  94. #define IRQ_TIMER2		BFIN_IRQ(88)	/* Timer 2 Interrupt */
    95. 

  95. #define IRQ_TIMER3		BFIN_IRQ(89)	/* Timer 3 Interrupt */
    96. 

  96. #define IRQ_TIMER4		BFIN_IRQ(90)	/* Timer 4 Interrupt */
    97. 

  97. #define IRQ_TIMER5		BFIN_IRQ(91)	/* Timer 5 Interrupt */
    98. 

  98. #define IRQ_TIMER6		BFIN_IRQ(92)	/* Timer 6 Interrupt */
    99. 

  99. #define IRQ_TIMER7		BFIN_IRQ(93)	/* Timer 7 Interrupt */
    100. 

  100. #define IRQ_PINT2		BFIN_IRQ(94)	/* PINT2 Interrupt */
    101. 

  101. #define IRQ_PINT3		BFIN_IRQ(95)	/* PINT3 Interrupt */
    102. 

  102. 

  103. #define SYS_IRQS		IRQ_PINT3
    104. 

  104. 

  105. #define BFIN_PA_IRQ(x)		((x) + SYS_IRQS + 1)
    106. 

  106. #define IRQ_PA0			BFIN_PA_IRQ(0)
    107. 

  107. #define IRQ_PA1			BFIN_PA_IRQ(1)
    108. 

  108. #define IRQ_PA2			BFIN_PA_IRQ(2)
    109. 

  109. #define IRQ_PA3			BFIN_PA_IRQ(3)
    110. 

  110. #define IRQ_PA4			BFIN_PA_IRQ(4)
    111. 

  111. #define IRQ_PA5			BFIN_PA_IRQ(5)
    112. 

  112. #define IRQ_PA6			BFIN_PA_IRQ(6)
    113. 

  113. #define IRQ_PA7			BFIN_PA_IRQ(7)
    114. 

  114. #define IRQ_PA8			BFIN_PA_IRQ(8)
    115. 

  115. #define IRQ_PA9			BFIN_PA_IRQ(9)
    116. 

  116. #define IRQ_PA10		BFIN_PA_IRQ(10)
    117. 

  117. #define IRQ_PA11		BFIN_PA_IRQ(11)
    118. 

  118. #define IRQ_PA12		BFIN_PA_IRQ(12)
    119. 

  119. #define IRQ_PA13		BFIN_PA_IRQ(13)
    120. 

  120. #define IRQ_PA14		BFIN_PA_IRQ(14)
    121. 

  121. #define IRQ_PA15		BFIN_PA_IRQ(15)
    122. 

  122. 

  123. #define BFIN_PB_IRQ(x)		((x) + IRQ_PA15 + 1)
    124. 

  124. #define IRQ_PB0			BFIN_PB_IRQ(0)
    125. 

  125. #define IRQ_PB1			BFIN_PB_IRQ(1)
    126. 

  126. #define IRQ_PB2			BFIN_PB_IRQ(2)
    127. 

  127. #define IRQ_PB3			BFIN_PB_IRQ(3)
    128. 

  128. #define IRQ_PB4			BFIN_PB_IRQ(4)
    129. 

  129. #define IRQ_PB5			BFIN_PB_IRQ(5)
    130. 

  130. #define IRQ_PB6			BFIN_PB_IRQ(6)
    131. 

  131. #define IRQ_PB7			BFIN_PB_IRQ(7)
    132. 

  132. #define IRQ_PB8			BFIN_PB_IRQ(8)
    133. 

  133. #define IRQ_PB9			BFIN_PB_IRQ(9)
    134. 

  134. #define IRQ_PB10		BFIN_PB_IRQ(10)
    135. 

  135. #define IRQ_PB11		BFIN_PB_IRQ(11)
    136. 

  136. #define IRQ_PB12		BFIN_PB_IRQ(12)
    137. 

  137. #define IRQ_PB13		BFIN_PB_IRQ(13)
    138. 

  138. #define IRQ_PB14		BFIN_PB_IRQ(14)
    139. 

  139. #define IRQ_PB15		BFIN_PB_IRQ(15)		/* N/A */
    140. 

  140. 

  141. #define BFIN_PC_IRQ(x)		((x) + IRQ_PB15 + 1)
    142. 

  142. #define IRQ_PC0			BFIN_PC_IRQ(0)
    143. 

  143. #define IRQ_PC1			BFIN_PC_IRQ(1)
    144. 

  144. #define IRQ_PC2			BFIN_PC_IRQ(2)
    145. 

  145. #define IRQ_PC3			BFIN_PC_IRQ(3)
    146. 

  146. #define IRQ_PC4			BFIN_PC_IRQ(4)
    147. 

  147. #define IRQ_PC5			BFIN_PC_IRQ(5)
    148. 

  148. #define IRQ_PC6			BFIN_PC_IRQ(6)
    149. 

  149. #define IRQ_PC7			BFIN_PC_IRQ(7)
    150. 

  150. #define IRQ_PC8			BFIN_PC_IRQ(8)
    151. 

  151. #define IRQ_PC9			BFIN_PC_IRQ(9)
    152. 

  152. #define IRQ_PC10		BFIN_PC_IRQ(10)
    153. 

  153. #define IRQ_PC11		BFIN_PC_IRQ(11)
    154.