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thermalAnalysisOfCable
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influenceAnalysisOfCableAging.h

influenceAnalysisOfCableAging.h 4.1 KB
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  1. /*
    2. 

  2.  * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009-2010 Texas Instruments, Inc.
    5. 

  5.  *
    6. 

  6.  * Benoit Cousson (b-cousson@ti.com)
    7. 

  7.  * Santosh Shilimkar (santosh.shilimkar@ti.com)
    8. 

  8.  *
    9. 

  9.  * This file is automatically generated from the OMAP hardware databases.
    10. 

  10.  * We respectfully ask that any modifications to this file be coordinated
    11. 

  11.  * with the public linux-omap@vger.kernel.org mailing list and the
    12. 

  12.  * authors above to ensure that the autogeneration scripts are kept
    13. 

  13.  * up-to-date with the file contents.
    14. 

  14.  *
    15. 

  15.  * This program is free software; you can redistribute it and/or modify
    16. 

  16.  * it under the terms of the GNU General Public License version 2 as
    17. 

  17.  * published by the Free Software Foundation.
    18. 

  18.  */
    19. 

  19. 

  20. #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
    21. 

  21. #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
    22. 

  22. 

  23. 

  24. /* Base address */
    25. 

  25. #define OMAP4_CTRL_MODULE_PAD_CORE				0x4a100000
    26. 

  26. 

  27. /* Registers offset */
    28. 

  28. #define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION			0x0000
    29. 

  29. #define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO			0x0004
    30. 

  30. #define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG			0x0010
    31. 

  31. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0	0x01d8
    32. 

  32. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1	0x01dc
    33. 

  33. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2	0x01e0
    34. 

  34. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3	0x01e4
    35. 

  35. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4	0x01e8
    36. 

  36. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5	0x01ec
    37. 

  37. #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6	0x01f0
    38. 

  38. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL	0x05a0
    39. 

  39. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE		0x05a4
    40. 

  40. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0	0x05a8
    41. 

  41. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1	0x05ac
    42. 

  42. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0	0x05b0
    43. 

  43. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1	0x05b4
    44. 

  44. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0	0x05b8
    45. 

  45. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1	0x05bc
    46. 

  46. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2	0x05c0
    47. 

  47. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC		0x05c4
    48. 

  48. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS		0x05c8
    49. 

  49. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE		0x0600
    50. 

  50. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0		0x0604
    51. 

  51. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX		0x0608
    52. 

  52. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC		0x060c
    53. 

  53. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY		0x0610
    54. 

  54. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2			0x0614
    55. 

  55. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY		0x0618
    56. 

  56. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP		0x061c
    57. 

  57. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE		0x0620
    58. 

  58. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1		0x0624
    59. 

  59. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1			0x0628
    60. 

  60. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI			0x062c
    61. 

  61. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB			0x0630
    62. 

  62. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ			0x0634
    63. 

  63. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0		0x0638
    64. 

  64. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1		0x063c
    65. 

  65. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2		0x0640
    66. 

  66. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3		0x0644
    67. 

  67. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0		0x0648
    68. 

  68. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1		0x064c
    69. 

  69. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2		0x0650
    70. 

  70. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3		0x0654
    71. 

  71. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD		0x0658
    72. 

  72. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C			0x065c
    73. 

  73. #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW	0x0660
    74. 

  74. #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R		0x0664
    75. 

  75. #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0	0x0668
    76. 

  76. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1		0x0700
    77. 

  77. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2		0x0704
    78. 

  78. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3		0x0708
    79. 

  79. #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4		0x070c
    80. 

  80. 

  81. /* Registers shifts and masks */
    82. 

  82. 

  83. /* IP_REVISION */
    84.