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synchronousMemoryDatabase.h

synchronousMemoryDatabase.h 25 KB
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  1. /*
    2. 

  2.  * Copyright 2005-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF537_H
    8. 

  8. #define _DEF_BF537_H
    9. 

  9. 

  10. /* Include all MMR and bit defines common to BF534 */
    11. 

  11. #include "defBF534.h"
    12. 

  12. 

  13. /************************************************************************************
    14. 

  14. ** Define EMAC Section Unique to BF536/BF537
    15. 

  15. *************************************************************************************/
    16. 

  16. 

  17. /* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF)										*/
    18. 

  18. #define	EMAC_OPMODE			0xFFC03000	/* Operating Mode Register                                                              */
    19. 

  19. #define EMAC_ADDRLO			0xFFC03004	/* Address Low (32 LSBs) Register                                               */
    20. 

  20. #define EMAC_ADDRHI			0xFFC03008	/* Address High (16 MSBs) Register                                              */
    21. 

  21. #define EMAC_HASHLO			0xFFC0300C	/* Multicast Hash Table Low (Bins 31-0) Register                */
    22. 

  22. #define EMAC_HASHHI			0xFFC03010	/* Multicast Hash Table High (Bins 63-32) Register              */
    23. 

  23. #define EMAC_STAADD			0xFFC03014	/* Station Management Address Register                                  */
    24. 

  24. #define EMAC_STADAT			0xFFC03018	/* Station Management Data Register                                     */
    25. 

  25. #define EMAC_FLC			0xFFC0301C	/* Flow Control Register                                                                */
    26. 

  26. #define EMAC_VLAN1			0xFFC03020	/* VLAN1 Tag Register                                                                   */
    27. 

  27. #define EMAC_VLAN2			0xFFC03024	/* VLAN2 Tag Register                                                                   */
    28. 

  28. #define EMAC_WKUP_CTL		0xFFC0302C	/* Wake-Up Control/Status Register                                              */
    29. 

  29. #define EMAC_WKUP_FFMSK0	0xFFC03030	/* Wake-Up Frame Filter 0 Byte Mask Register                    */
    30. 

  30. #define EMAC_WKUP_FFMSK1	0xFFC03034	/* Wake-Up Frame Filter 1 Byte Mask Register                    */
    31. 

  31. #define EMAC_WKUP_FFMSK2	0xFFC03038	/* Wake-Up Frame Filter 2 Byte Mask Register                    */
    32. 

  32. #define EMAC_WKUP_FFMSK3	0xFFC0303C	/* Wake-Up Frame Filter 3 Byte Mask Register                    */
    33. 

  33. #define EMAC_WKUP_FFCMD		0xFFC03040	/* Wake-Up Frame Filter Commands Register                               */
    34. 

  34. #define EMAC_WKUP_FFOFF		0xFFC03044	/* Wake-Up Frame Filter Offsets Register                                */
    35. 

  35. #define EMAC_WKUP_FFCRC0	0xFFC03048	/* Wake-Up Frame Filter 0,1 CRC-16 Register                             */
    36. 

  36. #define EMAC_WKUP_FFCRC1	0xFFC0304C	/* Wake-Up Frame Filter 2,3 CRC-16 Register                             */
    37. 

  37. 

  38. #define	EMAC_SYSCTL			0xFFC03060	/* EMAC System Control Register                                                 */
    39. 

  39. #define EMAC_SYSTAT			0xFFC03064	/* EMAC System Status Register                                                  */
    40. 

  40. #define EMAC_RX_STAT		0xFFC03068	/* RX Current Frame Status Register                                             */
    41. 

  41. #define EMAC_RX_STKY		0xFFC0306C	/* RX Sticky Frame Status Register                                              */
    42. 

  42. #define EMAC_RX_IRQE		0xFFC03070	/* RX Frame Status Interrupt Enables Register                   */
    43. 

  43. #define EMAC_TX_STAT		0xFFC03074	/* TX Current Frame Status Register                                             */
    44. 

  44. #define EMAC_TX_STKY		0xFFC03078	/* TX Sticky Frame Status Register                                              */
    45. 

  45. #define EMAC_TX_IRQE		0xFFC0307C	/* TX Frame Status Interrupt Enables Register                   */
    46. 

  46. 

  47. #define EMAC_MMC_CTL		0xFFC03080	/* MMC Counter Control Register                                                 */
    48. 

  48. #define EMAC_MMC_RIRQS		0xFFC03084	/* MMC RX Interrupt Status Register                                             */
    49. 

  49. #define EMAC_MMC_RIRQE		0xFFC03088	/* MMC RX Interrupt Enables Register                                    */
    50. 

  50. #define EMAC_MMC_TIRQS		0xFFC0308C	/* MMC TX Interrupt Status Register                                             */
    51. 

  51. #define EMAC_MMC_TIRQE		0xFFC03090	/* MMC TX Interrupt Enables Register                                    */
    52. 

  52. 

  53. #define EMAC_RXC_OK			0xFFC03100	/* RX Frame Successful Count                                                    */
    54. 

  54. #define EMAC_RXC_FCS		0xFFC03104	/* RX Frame FCS Failure Count                                                   */
    55. 

  55. #define EMAC_RXC_ALIGN		0xFFC03108	/* RX Alignment Error Count                                                             */
    56. 

  56. #define EMAC_RXC_OCTET		0xFFC0310C	/* RX Octets Successfully Received Count                                */
    57. 

  57. #define EMAC_RXC_DMAOVF		0xFFC03110	/* Internal MAC Sublayer Error RX Frame Count                   */
    58. 

  58. #define EMAC_RXC_UNICST		0xFFC03114	/* Unicast RX Frame Count                                                               */
    59. 

  59. #define EMAC_RXC_MULTI		0xFFC03118	/* Multicast RX Frame Count                                                             */
    60. 

  60. #define EMAC_RXC_BROAD		0xFFC0311C	/* Broadcast RX Frame Count                                                             */
    61. 

  61. #define EMAC_RXC_LNERRI		0xFFC03120	/* RX Frame In Range Error Count                                                */
    62. 

  62. #define EMAC_RXC_LNERRO		0xFFC03124	/* RX Frame Out Of Range Error Count                                    */
    63. 

  63. #define EMAC_RXC_LONG		0xFFC03128	/* RX Frame Too Long Count                                                              */
    64. 

  64. #define EMAC_RXC_MACCTL		0xFFC0312C	/* MAC Control RX Frame Count                                                   */
    65. 

  65. #define EMAC_RXC_OPCODE		0xFFC03130	/* Unsupported Op-Code RX Frame Count                                   */
    66. 

  66. #define EMAC_RXC_PAUSE		0xFFC03134	/* MAC Control Pause RX Frame Count                                             */
    67. 

  67. #define EMAC_RXC_ALLFRM		0xFFC03138	/* Overall RX Frame Count                                                               */
    68. 

  68. #define EMAC_RXC_ALLOCT		0xFFC0313C	/* Overall RX Octet Count                                                               */
    69. 

  69. #define EMAC_RXC_TYPED		0xFFC03140	/* Type/Length Consistent RX Frame Count                                */
    70. 

  70. #define EMAC_RXC_SHORT		0xFFC03144	/* RX Frame Fragment Count - Byte Count x < 64                  */
    71. 

  71. #define EMAC_RXC_EQ64		0xFFC03148	/* Good RX Frame Count - Byte Count x = 64                              */
    72. 

  72. #define EMAC_RXC_LT128		0xFFC0314C	/* Good RX Frame Count - Byte Count  64 <= x < 128              */
    73. 

  73. #define EMAC_RXC_LT256		0xFFC03150	/* Good RX Frame Count - Byte Count 128 <= x < 256              */
    74. 

  74. #define EMAC_RXC_LT512		0xFFC03154	/* Good RX Frame Count - Byte Count 256 <= x < 512              */
    75. 

  75. #define EMAC_RXC_LT1024		0xFFC03158	/* Good RX Frame Count - Byte Count 512 <= x < 1024             */
    76. 

  76. #define EMAC_RXC_GE1024		0xFFC0315C	/* Good RX Frame Count - Byte Count x >= 1024                   */
    77. 

  77. 

  78. #define EMAC_TXC_OK			0xFFC03180	/* TX Frame Successful Count                                                    */
    79. 

  79. #define EMAC_TXC_1COL		0xFFC03184	/* TX Frames Successful After Single Collision Count    */
    80. 

  80. #define EMAC_TXC_GT1COL		0xFFC03188	/* TX Frames Successful After Multiple Collisions Count */
    81. 

  81. #define EMAC_TXC_OCTET		0xFFC0318C	/* TX Octets Successfully Received Count                                */
    82. 

  82. #define EMAC_TXC_DEFER		0xFFC03190	/* TX Frame Delayed Due To Busy Count                                   */
    83. 

  83. #define EMAC_TXC_LATECL		0xFFC03194	/* Late TX Collisions Count                                                             */
    84. 

  84. #define EMAC_TXC_XS_COL		0xFFC03198	/* TX Frame Failed Due To Excessive Collisions Count    */
    85. 

  85. #define EMAC_TXC_DMAUND		0xFFC0319C	/* Internal MAC Sublayer Error TX Frame Count                   */
    86. 

  86. #define EMAC_TXC_CRSERR		0xFFC031A0	/* Carrier Sense Deasserted During TX Frame Count               */
    87. 

  87. #define EMAC_TXC_UNICST		0xFFC031A4	/* Unicast TX Frame Count                                                               */
    88. 

  88. #define EMAC_TXC_MULTI		0xFFC031A8	/* Multicast TX Frame Count                                                             */
    89. 

  89. #define EMAC_TXC_BROAD		0xFFC031AC	/* Broadcast TX Frame Count                                                             */
    90. 

  90. #define EMAC_TXC_XS_DFR		0xFFC031B0	/* TX Frames With Excessive Deferral Count                              */
    91. 

  91. #define EMAC_TXC_MACCTL		0xFFC031B4	/* MAC Control TX Frame Count                                                   */
    92. 

  92. #define EMAC_TXC_ALLFRM		0xFFC031B8	/* Overall TX Frame Count                                                               */
    93. 

  93. #define EMAC_TXC_ALLOCT		0xFFC031BC	/* Overall TX Octet Count                                                               */
    94. 

  94. #define EMAC_TXC_EQ64		0xFFC031C0	/* Good TX Frame Count - Byte Count x = 64                              */
    95. 

  95. #define EMAC_TXC_LT128		0xFFC031C4	/* Good TX Frame Count - Byte Count  64 <= x < 128              */
    96. 

  96. #define EMAC_TXC_LT256		0xFFC031C8	/* Good TX Frame Count - Byte Count 128 <= x < 256              */
    97. 

  97. #define EMAC_TXC_LT512		0xFFC031CC	/* Good TX Frame Count - Byte Count 256 <= x < 512              */
    98. 

  98. #define EMAC_TXC_LT1024		0xFFC031D0	/* Good TX Frame Count - Byte Count 512 <= x < 1024             */
    99. 

  99. #define EMAC_TXC_GE1024		0xFFC031D4	/* Good TX Frame Count - Byte Count x >= 1024                   */
    100. 

  100. #define EMAC_TXC_ABORT		0xFFC031D8	/* Total TX Frames Aborted Count                                                */
    101. 

  101. 

  102. /* Listing for IEEE-Supported Count Registers																	*/
    103. 

  103. #define FramesReceivedOK				EMAC_RXC_OK	/* RX Frame Successful Count                                                    */
    104. 

  104. #define FrameCheckSequenceErrors		EMAC_RXC_FCS	/* RX Frame FCS Failure Count                                                   */
    105. 

  105. #define AlignmentErrors					EMAC_RXC_ALIGN	/* RX Alignment Error Count                                                             */
    106. 

  106. #define OctetsReceivedOK				EMAC_RXC_OCTET	/* RX Octets Successfully Received Count                                */
    107. 

  107. #define FramesLostDueToIntMACRcvError	EMAC_RXC_DMAOVF	/* Internal MAC Sublayer Error RX Frame Count                   */
    108. 

  108. #define UnicastFramesReceivedOK			EMAC_RXC_UNICST	/* Unicast RX Frame Count                                                               */
    109. 

  109. #define MulticastFramesReceivedOK		EMAC_RXC_MULTI	/* Multicast RX Frame Count                                                             */
    110. 

  110. #define BroadcastFramesReceivedOK		EMAC_RXC_BROAD	/* Broadcast RX Frame Count                                                             */
    111. 

  111. #define InRangeLengthErrors				EMAC_RXC_LNERRI	/* RX Frame In Range Error Count                                                */
    112. 

  112. #define OutOfRangeLengthField			EMAC_RXC_LNERRO	/* RX Frame Out Of Range Error Count                                    */
    113. 

  113. #define FrameTooLongErrors				EMAC_RXC_LONG	/* RX Frame Too Long Count                                                              */
    114. 

  114. #define MACControlFramesReceived		EMAC_RXC_MACCTL	/* MAC Control RX Frame Count                                                   */
    115. 

  115. #define UnsupportedOpcodesReceived		EMAC_RXC_OPCODE	/* Unsupported Op-Code RX Frame Count                                   */
    116. 

  116. #define PAUSEMACCtrlFramesReceived		EMAC_RXC_PAUSE	/* MAC Control Pause RX Frame Count                                             */
    117. 

  117. #define FramesReceivedAll				EMAC_RXC_ALLFRM	/* Overall RX Frame Count                                                               */
    118. 

  118. #define OctetsReceivedAll				EMAC_RXC_ALLOCT	/* Overall RX Octet Count                                                               */
    119. 

  119. #define TypedFramesReceived				EMAC_RXC_TYPED	/* Type/Length Consistent RX Frame Count                                */
    120. 

  120. #define FramesLenLt64Received			EMAC_RXC_SHORT	/* RX Frame Fragment Count - Byte Count x < 64                  */
    121. 

  121. #define FramesLenEq64Received			EMAC_RXC_EQ64	/* Good RX Frame Count - Byte Count x = 64                              */
    122. 

  122. #define FramesLen65_127Received			EMAC_RXC_LT128	/* Good RX Frame Count - Byte Count  64 <= x < 128              */
    123. 

  123. #define FramesLen128_255Received		EMAC_RXC_LT256	/* Good RX Frame Count - Byte Count 128 <= x < 256              */
    124. 

  124. #define FramesLen256_511Received		EMAC_RXC_LT512	/* Good RX Frame Count - Byte Count 256 <= x < 512              */
    125. 

  125. #define FramesLen512_1023Received		EMAC_RXC_LT1024	/* Good RX Frame Count - Byte Count 512 <= x < 1024             */
    126. 

  126. #define FramesLen1024_MaxReceived		EMAC_RXC_GE1024	/* Good RX Frame Count - Byte Count x >= 1024                   */
    127. 

  127. 

  128. #define FramesTransmittedOK				EMAC_TXC_OK	/* TX Frame Successful Count                                                    */
    129. 

  129. #define SingleCollisionFrames			EMAC_TXC_1COL	/* TX Frames Successful After Single Collision Count    */
    130. 

  130. #define MultipleCollisionFrames			EMAC_TXC_GT1COL	/* TX Frames Successful After Multiple Collisions Count */
    131. 

  131. #define OctetsTransmittedOK				EMAC_TXC_OCTET	/* TX Octets Successfully Received Count                                */
    132. 

  132. #define FramesWithDeferredXmissions		EMAC_TXC_DEFER	/* TX Frame Delayed Due To Busy Count                                   */
    133. 

  133. #define LateCollisions					EMAC_TXC_LATECL	/* Late TX Collisions Count                                                             */
    134. 

  134. #define FramesAbortedDueToXSColls		EMAC_TXC_XS_COL	/* TX Frame Failed Due To Excessive Collisions Count    */
    135. 

  135. #define FramesLostDueToIntMacXmitError	EMAC_TXC_DMAUND	/* Internal MAC Sublayer Error TX Frame Count                   */
    136. 

  136. #define CarrierSenseErrors				EMAC_TXC_CRSERR	/* Carrier Sense Deasserted During TX Frame Count               */
    137. 

  137. #define UnicastFramesXmittedOK			EMAC_TXC_UNICST	/* Unicast TX Frame Count                                                               */
    138. 

  138. #define MulticastFramesXmittedOK		EMAC_TXC_MULTI	/* Multicast TX Frame Count                                                             */
    139. 

  139. #define BroadcastFramesXmittedOK		EMAC_TXC_BROAD	/* Broadcast TX Frame Count                                                             */
    140. 

  140. #define FramesWithExcessiveDeferral		EMAC_TXC_XS_DFR	/* TX Frames With Excessive Deferral Count                              */
    141. 

  141. #define MACControlFramesTransmitted		EMAC_TXC_MACCTL	/* MAC Control TX Frame Count                                                   */
    142. 

  142. #define FramesTransmittedAll			EMAC_TXC_ALLFRM	/* Overall TX Frame Count                                                               */
    143. 

  143. #define OctetsTransmittedAll			EMAC_TXC_ALLOCT	/* Overall TX Octet Count                                                               */
    144. 

  144. #define FramesLenEq64Transmitted		EMAC_TXC_EQ64	/* Good TX Frame Count - Byte Count x = 64                              */
    145. 

  145. #define FramesLen65_127Transmitted		EMAC_TXC_LT128	/* Good TX Frame Count - Byte Count  64 <= x < 128              */
    146. 

  146. #define FramesLen128_255Transmitted		EMAC_TXC_LT256	/* Good TX Frame Count - Byte Count 128 <= x < 256              */
    147. 

  147. #define FramesLen256_511Transmitted		EMAC_TXC_LT512	/* Good TX Frame Count - Byte Count 256 <= x < 512              */
    148. 

  148. #define FramesLen512_1023Transmitted	EMAC_TXC_LT1024	/* Good TX Frame Count - Byte Count 512 <= x < 1024             */
    149. 

  149. #define FramesLen1024_MaxTransmitted	EMAC_TXC_GE1024	/* Good TX Frame Count - Byte Count x >= 1024                   */
    150. 

  150. #define TxAbortedFrames					EMAC_TXC_ABORT	/* Total TX Frames Aborted Count                                                */
    151. 

  151. 

  152. /***********************************************************************************
    153. 

  153. ** System MMR Register Bits And Macros
    154. 

  154. **
    155. 

  155. ** Disclaimer:	All macros are intended to make C and Assembly code more readable.
    156. 

  156. **				Use these macros carefully, as any that do left shifts for field
    157. 

  157. **				depositing will result in the lower order bits being destroyed.  Any
    158. 

  158. **				macro that shifts left to properly position the bit-field should be
    159. 

  159. **				used as part of an OR to initialize a register and NOT as a dynamic
    160. 

  160. **				modifier UNLESS the lower order bits are saved and ORed back in when
    161. 

  161. **				the macro is used.
    162. 

  162. *************************************************************************************/
    163. 

  163. /************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
    164. 

  164. /* EMAC_OPMODE Masks																*/
    165. 

  165. #define	RE			0x00000001	/* Receiver Enable                                                                      */
    166. 

  166. #define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames          */
    167. 

  167. #define	HU			0x00000010	/* Hash Filter Unicast Address                                          */
    168. 

  168. #define	HM			0x00000020	/* Hash Filter Multicast Address                                        */
    169. 

  169. #define	PAM			0x00000040	/* Pass-All-Multicast Mode Enable                                       */
    170. 

  170. #define	PR			0x00000080	/* Promiscuous Mode Enable                                                      */
    171. 

  171. #define	IFE			0x00000100	/* Inverse Filtering Enable                                                     */
    172. 

  172. #define	DBF			0x00000200	/* Disable Broadcast Frame Reception                            */
    173. 

  173. #define	PBF			0x00000400	/* Pass Bad Frames Enable                                                       */
    174. 

  174. #define	PSF			0x00000800	/* Pass Short Frames Enable                                                     */
    175. 

  175. #define	RAF			0x00001000	/* Receive-All Mode                                                                     */
    176. 

  176. #define	TE			0x00010000	/* Transmitter Enable                                                           */
    177. 

  177. #define	DTXPAD		0x00020000	/* Disable Automatic TX Padding                                         */
    178. 

  178. #define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation                          */
    179. 

  179. #define	DC			0x00080000	/* Deferral Check                                                                       */
    180. 

  180. #define	BOLMT		0x00300000	/* Back-Off Limit                                                                       */
    181. 

  181. #define	BOLMT_10	0x00000000	/*              10-bit range                                                            */
    182. 

  182. #define	BOLMT_8		0x00100000	/*              8-bit range                                                                     */
    183. 

  183. #define	BOLMT_4		0x00200000	/*              4-bit range                                                                     */
    184. 

  184. #define	BOLMT_1		0x00300000	/*              1-bit range                                                                     */
    185. 

  185. #define	DRTY		0x00400000	/* Disable TX Retry On Collision                                        */
    186. 

  186. #define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision                            */
    187. 

  187. #define	RMII		0x01000000	/* RMII/MII* Mode                                                                       */
    188. 

  188. #define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*)         */
    189. 

  189. #define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*)                                      */
    190. 

  190. #define	LB			0x08000000	/* Internal Loopback Enable                                                     */
    191. 

  191. #define	DRO			0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode)        */
    192. 

  192. 

  193. /* EMAC_STAADD Masks																*/
    194. 

  194. #define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat      */
    195. 

  195. #define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*)      */
    196. 

  196. #define	STADISPRE	0x00000004	/* Disable Preamble Generation                                          */
    197. 

  197. #define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable          */
    198. 

  198. #define	REGAD		0x000007C0	/* STA Register Address                                                         */
    199. 

  199. #define	PHYAD		0x0000F800	/* PHY Device Address                                                           */
    200. 

  200. 

  201. #define	SET_REGAD(x)	(((x)&0x1F)<<  6 )	/* Set STA Register Address                             */
    202. 

  202. #define	SET_PHYAD(x)	(((x)&0x1F)<< 11 )	/* Set PHY Device Address                               */
    203. 

  203. 

  204. /* EMAC_STADAT Mask											*/
    205. 

  205. #define	STADATA		0x0000FFFF	/* Station Management Data      */
    206. 

  206. 

  207. /* EMAC_FLC Masks																	*/
    208. 

  208. #define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status         */
    209. 

  209. #define	FLCE		0x00000002	/* Flow Control Enable                                                          */
    210. 

  210. #define	PCF			0x00000004	/* Pass Control Frames                                                          */
    211. 

  211. #define	BKPRSEN		0x00000008	/* Enable Backpressure                                                          */
    212. 

  212. #define	FLCPAUSE	0xFFFF0000	/* Pause Time                                                                           */
    213. 

  213. 

  214. #define	SET_FLCPAUSE(x)	(((x)&0xFFFF)<< 16)	/* Set Pause Time                                               */
    215. 

  215. 

  216. /* EMAC_WKUP_CTL Masks																*/
    217. 

  217. #define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames                                                       */
    218. 

  218. #define	MPKE		0x00000002	/* Magic Packet Enable                                                          */
    219. 

  219. #define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable                                          */
    220. 

  220. #define	GUWKE		0x00000008	/* Global Unicast Wake Enable                                           */
    221. 

  221. #define	MPKS		0x00000020	/* Magic Packet Received Status                                         */
    222. 

  222. #define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0           */
    223. 

  223. 

  224. /* EMAC_WKUP_FFCMD Masks															*/
    225. 

  225. #define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0                                                      */
    226. 

  226. #define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
    227. 

  227. #define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1                                                      */
    228. 

  228. #define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
    229. 

  229. #define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2                                                      */
    230. 

  230. #define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
    231. 

  231. #define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3                                                      */
    232. 

  232. #define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
    233. 

  233. 

  234. /* EMAC_WKUP_FFOFF Masks															*/
    235. 

  235. #define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset                                      */
    236. 

  236. #define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset                                      */
    237. 

  237. #define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset                                      */
    238. 

  238. #define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset                                      */
    239. 

  239. 

  240. #define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 )	/* Set Wake-Up Filter 0 Byte Offset           */
    241. 

  241. #define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 )	/* Set Wake-Up Filter 1 Byte Offset           */
    242. 

  242. #define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 )	/* Set Wake-Up Filter 2 Byte Offset           */
    243. 

  243. #define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 )	/* Set Wake-Up Filter 3 Byte Offset           */
    244. 

  244. /* Set ALL Offsets																	*/
    245. 

  245. #define	SET_WF_OFFS(x0,x1,x2,x3) 	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
    246. 

  246. 

  247. /* EMAC_WKUP_FFCRC0 Masks															*/
    248. 

  248. #define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC                                         */
    249. 

  249. #define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC                                         */
    250. 

  250. 

  251. #define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 )	/* Set Wake-Up Filter 0 Target CRC         */
    252. 

  252. #define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 )	/* Set Wake-Up Filter 1 Target CRC         */
    253. 

  253. 

  254. /* EMAC_WKUP_FFCRC1 Masks															*/
    255. 

  255. #define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC                                         */
    256. 

  256. #define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC                                         */
    257. 

  257. 

  258. #define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 )	/* Set Wake-Up Filter 2 Target CRC         */
    259. 

  259. #define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 )	/* Set Wake-Up Filter 3 Target CRC         */
    260. 

  260. 

  261. /* EMAC_SYSCTL Masks																*/
    262. 

  262. #define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable                                                     */
    263. 

  263. #define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*)         */
    264. 

  264. #define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation         */
    265. 

  265. #define	TXDWA		0x00000010	/* Transmit Frame DMA Word Alignment (Odd/Even*)        */
    266. 

  266. #define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */
    267. 

  267. 

  268. #define	SET_MDCDIV(x)	(((x)&0x3F)<< 8)	/* Set MDC Clock Divisor                                */
    269. 

  269. 

  270. /* EMAC_SYSTAT Masks															*/
    271. 

  271. #define	PHYINT		0x00000001	/* PHY_INT Interrupt Status                                             */
    272. 

  272. #define	MMCINT		0x00000002	/* MMC Counter Interrupt Status                                 */
    273. 

  273. #define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status                             */
    274. 

  274. #define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status                             */
    275. 

  275. #define	WAKEDET		0x00000010	/* Wake-Up Detected Status                                              */
    276. 

  276. #define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status                                */
    277. 

  277. #define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status                                */
    278. 

  278. #define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status  */
    279. 

  279. 

  280. /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks							*/
    281. 

  281. #define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes                                                */
    282.