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waterHeterogeneousDataSynchronization
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externalConnectionMonitoring
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commandProcessing.h

commandProcessing.h 6.4 KB
Cronologia Originale

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  1. /*
    2. 

  2.  * Copyright 2005-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF561_H
    8. 

  8. #define _DEF_BF561_H
    9. 

  9. 

  10. /*********************************************************************************** */
    11. 

  11. /* System MMR Register Map */
    12. 

  12. /*********************************************************************************** */
    13. 

  13. 

  14. /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
    15. 

  15. 

  16. #define PLL_CTL                0xFFC00000	/* PLL Control register (16-bit) */
    17. 

  17. #define PLL_DIV			        0xFFC00004	/* PLL Divide Register (16-bit) */
    18. 

  18. #define VR_CTL			        0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    19. 

  19. #define PLL_STAT               0xFFC0000C	/* PLL Status register (16-bit) */
    20. 

  20. #define PLL_LOCKCNT            0xFFC00010	/* PLL Lock Count register (16-bit) */
    21. 

  21. #define CHIPID                 0xFFC00014       /* Chip ID Register */
    22. 

  22. 

  23. /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
    24. 

  24. #define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
    25. 

  25. #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
    26. 

  26. #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
    27. 

  27. #define RESET_SOFTWARE          (SWRST_OCCURRED)
    28. 

  28. 

  29. /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
    30. 

  30. #define SWRST                   0xFFC00100	/* Software Reset register */
    31. 

  31. #define SYSCR                   0xFFC00104	/* System Reset Configuration register */
    32. 

  32. #define SIC_RVECT               0xFFC00108	/* SIC Reset Vector Address Register */
    33. 

  33. #define SIC_IMASK0              0xFFC0010C	/* SIC Interrupt Mask register 0 */
    34. 

  34. #define SIC_IMASK1              0xFFC00110	/* SIC Interrupt Mask register 1 */
    35. 

  35. #define SIC_IAR0                0xFFC00124	/* SIC Interrupt Assignment Register 0 */
    36. 

  36. #define SIC_IAR1                0xFFC00128	/* SIC Interrupt Assignment Register 1 */
    37. 

  37. #define SIC_IAR2                0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
    38. 

  38. #define SIC_IAR3                0xFFC00130	/* SIC Interrupt Assignment Register 3 */
    39. 

  39. #define SIC_IAR4                0xFFC00134	/* SIC Interrupt Assignment Register 4 */
    40. 

  40. #define SIC_IAR5                0xFFC00138	/* SIC Interrupt Assignment Register 5 */
    41. 

  41. #define SIC_IAR6                0xFFC0013C	/* SIC Interrupt Assignment Register 6 */
    42. 

  42. #define SIC_IAR7                0xFFC00140	/* SIC Interrupt Assignment Register 7 */
    43. 

  43. #define SIC_ISR0                0xFFC00114	/* SIC Interrupt Status register 0 */
    44. 

  44. #define SIC_ISR1                0xFFC00118	/* SIC Interrupt Status register 1 */
    45. 

  45. #define SIC_IWR0                0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
    46. 

  46. #define SIC_IWR1                0xFFC00120	/* SIC Interrupt Wakeup-Enable register 1 */
    47. 

  47. 

  48. /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
    49. 

  49. #define SICB_SWRST              0xFFC01100	/* reserved */
    50. 

  50. #define SICB_SYSCR              0xFFC01104	/* reserved */
    51. 

  51. #define SICB_RVECT              0xFFC01108	/* SIC Reset Vector Address Register */
    52. 

  52. #define SICB_IMASK0             0xFFC0110C	/* SIC Interrupt Mask register 0 */
    53. 

  53. #define SICB_IMASK1             0xFFC01110	/* SIC Interrupt Mask register 1 */
    54. 

  54. #define SICB_IAR0               0xFFC01124	/* SIC Interrupt Assignment Register 0 */
    55. 

  55. #define SICB_IAR1               0xFFC01128	/* SIC Interrupt Assignment Register 1 */
    56. 

  56. #define SICB_IAR2               0xFFC0112C	/* SIC Interrupt Assignment Register 2 */
    57. 

  57. #define SICB_IAR3               0xFFC01130	/* SIC Interrupt Assignment Register 3 */
    58. 

  58. #define SICB_IAR4               0xFFC01134	/* SIC Interrupt Assignment Register 4 */
    59. 

  59. #define SICB_IAR5               0xFFC01138	/* SIC Interrupt Assignment Register 5 */
    60. 

  60. #define SICB_IAR6               0xFFC0113C	/* SIC Interrupt Assignment Register 6 */
    61. 

  61. #define SICB_IAR7               0xFFC01140	/* SIC Interrupt Assignment Register 7 */
    62. 

  62. #define SICB_ISR0               0xFFC01114	/* SIC Interrupt Status register 0 */
    63. 

  63. #define SICB_ISR1               0xFFC01118	/* SIC Interrupt Status register 1 */
    64. 

  64. #define SICB_IWR0               0xFFC0111C	/* SIC Interrupt Wakeup-Enable register 0 */
    65. 

  65. #define SICB_IWR1               0xFFC01120	/* SIC Interrupt Wakeup-Enable register 1 */
    66. 

  66. 

  67. /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
    68. 

  68. #define WDOGA_CTL 				0xFFC00200	/* Watchdog Control register */
    69. 

  69. #define WDOGA_CNT 				0xFFC00204	/* Watchdog Count register */
    70. 

  70. #define WDOGA_STAT 				0xFFC00208	/* Watchdog Status register */
    71. 

  71. 

  72. /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
    73. 

  73. #define WDOGB_CTL 				0xFFC01200	/* Watchdog Control register */
    74. 

  74. #define WDOGB_CNT 				0xFFC01204	/* Watchdog Count register */
    75. 

  75. #define WDOGB_STAT 				0xFFC01208	/* Watchdog Status register */
    76. 

  76. 

  77. /* UART Controller (0xFFC00400 - 0xFFC004FF) */
    78. 

  78. 

  79. /*
    80. 

  80.  * Because include/linux/serial_reg.h have defined UART_*,
    81. 

  81.  * So we define blackfin uart regs to BFIN_UART0_*.
    82. 

  82.  */
    83. 

  83. #define BFIN_UART_THR			0xFFC00400  /* Transmit Holding register */
    84. 

  84. #define BFIN_UART_RBR			0xFFC00400  /* Receive Buffer register */
    85. 

  85. #define BFIN_UART_DLL			0xFFC00400  /* Divisor Latch (Low-Byte) */
    86. 

  86. #define BFIN_UART_IER			0xFFC00404  /* Interrupt Enable Register */
    87. 

  87. #define BFIN_UART_DLH			0xFFC00404  /* Divisor Latch (High-Byte) */
    88. 

  88. #define BFIN_UART_IIR			0xFFC00408  /* Interrupt Identification Register */
    89. 

  89. #define BFIN_UART_LCR			0xFFC0040C  /* Line Control Register */
    90. 

  90. #define BFIN_UART_MCR			0xFFC00410  /* Modem Control Register */
    91. 

  91. #define BFIN_UART_LSR			0xFFC00414  /* Line Status Register */
    92. 

  92. #define BFIN_UART_MSR			0xFFC00418  /* Modem Status Register */
    93. 

  93. #define BFIN_UART_SCR			0xFFC0041C  /* SCR Scratch Register */
    94. 

  94. #define BFIN_UART_GCTL			0xFFC00424  /* Global Control Register */
    95. 

  95. 

  96. /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
    97. 

  97. #define SPI0_REGBASE          		0xFFC00500
    98. 

  98. #define SPI_CTL               		0xFFC00500	/* SPI Control Register */
    99. 

  99. #define SPI_FLG               		0xFFC00504	/* SPI Flag register */
    100. 

  100. #define SPI_STAT              		0xFFC00508	/* SPI Status register */
    101. 

  101. #define SPI_TDBR              		0xFFC0050C	/* SPI Transmit Data Buffer Register */
    102. 

  102. #define SPI_RDBR              		0xFFC00510	/* SPI Receive Data Buffer Register */
    103. 

  103. #define SPI_BAUD              		0xFFC00514	/* SPI Baud rate Register */
    104. 

  104. #define SPI_SHADOW            		0xFFC00518	/* SPI_RDBR Shadow Register */
    105. 

  105. 

  106. /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
    107. 

  107. #define TIMER0_CONFIG 				0xFFC00600	/* Timer0 Configuration register */
    108. 

  108. #define TIMER0_COUNTER 				0xFFC00604	/* Timer0 Counter register */
    109. 

  109. #define TIMER0_PERIOD 				0xFFC00608	/* Timer0 Period register */
    110.