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- /*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
- #ifndef _DEF_BF561_H
- #define _DEF_BF561_H
- /*********************************************************************************** */
- /* System MMR Register Map */
- /*********************************************************************************** */
- /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
- #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
- #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
- #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
- #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
- #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
- #define CHIPID 0xFFC00014 /* Chip ID Register */
- /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
- #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
- #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
- #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
- #define RESET_SOFTWARE (SWRST_OCCURRED)
- /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
- #define SWRST 0xFFC00100 /* Software Reset register */
- #define SYSCR 0xFFC00104 /* System Reset Configuration register */
- #define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
- #define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
- #define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
- #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
- #define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
- #define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
- #define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
- #define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
- #define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
- #define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
- #define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
- #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
- #define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
- #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
- #define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
- /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
- #define SICB_SWRST 0xFFC01100 /* reserved */
- #define SICB_SYSCR 0xFFC01104 /* reserved */
- #define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
- #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
- #define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
- #define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
- #define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
- #define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
- #define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
- #define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
- #define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
- #define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
- #define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
- #define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
- #define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
- #define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
- #define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
- /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
- #define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
- #define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
- #define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
- /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
- #define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
- #define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
- #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
- /* UART Controller (0xFFC00400 - 0xFFC004FF) */
- /*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
- #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
- #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
- #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
- #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
- #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
- #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
- #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
- #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
- #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
- #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
- #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
- #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
- /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
- #define SPI0_REGBASE 0xFFC00500
- #define SPI_CTL 0xFFC00500 /* SPI Control Register */
- #define SPI_FLG 0xFFC00504 /* SPI Flag register */
- #define SPI_STAT 0xFFC00508 /* SPI Status register */
- #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
- #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
- #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
- #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
- /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
- #define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
- #define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
- #define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
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