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aiot
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efDataPreprocessing
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dataProcessing
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dataPreprocessingThread.h

dataPreprocessingThread.h 2.3 KB
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  1. /*
    2. 

  2.  * Copyright 2008 Cavium Networks
    3. 

  3.  *
    4. 

  4.  * This file is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License, Version 2, as
    6. 

  6.  * published by the Free Software Foundation.
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef __MACH_BOARD_CNS3XXXH
    10. 

  10. #define __MACH_BOARD_CNS3XXXH
    11. 

  11. 

  12. /*
    13. 

  13.  * Memory map
    14. 

  14.  */
    15. 

  15. #define CNS3XXX_FLASH_BASE			0x10000000	/* Flash/SRAM Memory Bank 0 */
    16. 

  16. #define CNS3XXX_FLASH_SIZE			SZ_256M
    17. 

  17. 

  18. #define CNS3XXX_DDR2SDRAM_BASE			0x20000000	/* DDR2 SDRAM Memory */
    19. 

  19. 

  20. #define CNS3XXX_SPI_FLASH_BASE			0x60000000	/* SPI Serial Flash Memory */
    21. 

  21. 

  22. #define CNS3XXX_SWITCH_BASE			0x70000000	/* Switch and HNAT Control */
    23. 

  23. #define CNS3XXX_SWITCH_BASE_VIRT		0xFFF00000
    24. 

  24. 

  25. #define CNS3XXX_PPE_BASE			0x70001000	/* HANT	*/
    26. 

  26. #define CNS3XXX_PPE_BASE_VIRT			0xFFF50000
    27. 

  27. 

  28. #define CNS3XXX_EMBEDDED_SRAM_BASE		0x70002000	/* HANT Embedded SRAM */
    29. 

  29. #define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT		0xFFF60000
    30. 

  30. 

  31. #define CNS3XXX_SSP_BASE			0x71000000	/* Synchronous Serial Port - SPI/PCM/I2C */
    32. 

  32. #define CNS3XXX_SSP_BASE_VIRT			0xFFF01000
    33. 

  33. 

  34. #define CNS3XXX_DMC_BASE			0x72000000	/* DMC Control (DDR2 SDRAM) */
    35. 

  35. #define CNS3XXX_DMC_BASE_VIRT			0xFFF02000
    36. 

  36. 

  37. #define CNS3XXX_SMC_BASE			0x73000000	/* SMC Control */
    38. 

  38. #define CNS3XXX_SMC_BASE_VIRT			0xFFF03000
    39. 

  39. 

  40. #define SMC_MEMC_STATUS_OFFSET			0x000
    41. 

  41. #define SMC_MEMIF_CFG_OFFSET			0x004
    42. 

  42. #define SMC_MEMC_CFG_SET_OFFSET			0x008
    43. 

  43. #define SMC_MEMC_CFG_CLR_OFFSET			0x00C
    44. 

  44. #define SMC_DIRECT_CMD_OFFSET			0x010
    45. 

  45. #define SMC_SET_CYCLES_OFFSET			0x014
    46. 

  46. #define SMC_SET_OPMODE_OFFSET			0x018
    47. 

  47. #define SMC_REFRESH_PERIOD_0_OFFSET		0x020
    48. 

  48. #define SMC_REFRESH_PERIOD_1_OFFSET		0x024
    49. 

  49. #define SMC_SRAM_CYCLES0_0_OFFSET		0x100
    50. 

  50. #define SMC_NAND_CYCLES0_0_OFFSET		0x100
    51. 

  51. #define SMC_OPMODE0_0_OFFSET			0x104
    52. 

  52. #define SMC_SRAM_CYCLES0_1_OFFSET		0x120
    53. 

  53. #define SMC_NAND_CYCLES0_1_OFFSET		0x120
    54. 

  54. #define SMC_OPMODE0_1_OFFSET			0x124
    55. 

  55. #define SMC_USER_STATUS_OFFSET			0x200
    56. 

  56. #define SMC_USER_CONFIG_OFFSET			0x204
    57. 

  57. #define SMC_ECC_STATUS_OFFSET			0x300
    58. 

  58. #define SMC_ECC_MEMCFG_OFFSET			0x304
    59. 

  59. #define SMC_ECC_MEMCOMMAND1_OFFSET		0x308
    60. 

  60. #define SMC_ECC_MEMCOMMAND2_OFFSET		0x30C
    61. 

  61. #define SMC_ECC_ADDR0_OFFSET			0x310
    62. 

  62. #define SMC_ECC_ADDR1_OFFSET			0x314
    63. 

  63. #define SMC_ECC_VALUE0_OFFSET			0x318
    64. 

  64. #define SMC_ECC_VALUE1_OFFSET			0x31C
    65. 

  65. #define SMC_ECC_VALUE2_OFFSET			0x320
    66. 

  66. #define SMC_ECC_VALUE3_OFFSET			0x324
    67. 

  67. #define SMC_PERIPH_ID_0_OFFSET			0xFE0
    68. 

  68. #define SMC_PERIPH_ID_1_OFFSET			0xFE4
    69.