| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117 | /* * sh7372 Power management support * *  Copyright (C) 2011 Magnus Damm * * This file is subject to the terms and conditions of the GNU General Public * License.  See the file "COPYING" in the main directory of this archive * for more details. */#include <linux/pm.h>#include <linux/suspend.h>#include <linux/cpuidle.h>#include <linux/module.h>#include <linux/list.h>#include <linux/err.h>#include <linux/slab.h>#include <linux/pm_clock.h>#include <linux/platform_device.h>#include <linux/delay.h>#include <linux/irq.h>#include <linux/bitrev.h>#include <linux/console.h>#include <asm/cpuidle.h>#include <asm/io.h>#include <asm/tlbflush.h>#include <asm/suspend.h>#include <mach/common.h>#include <mach/sh7372.h>#include <mach/pm-rmobile.h>/* DBG */#define DBGREG1 IOMEM(0xe6100020)#define DBGREG9 IOMEM(0xe6100040)/* CPGA */#define SYSTBCR IOMEM(0xe6150024)#define MSTPSR0 IOMEM(0xe6150030)#define MSTPSR1 IOMEM(0xe6150038)#define MSTPSR2 IOMEM(0xe6150040)#define MSTPSR3 IOMEM(0xe6150048)#define MSTPSR4 IOMEM(0xe615004c)#define PLLC01STPCR IOMEM(0xe61500c8)/* SYSC */#define SBAR IOMEM(0xe6180020)#define WUPRMSK IOMEM(0xe6180028)#define WUPSMSK IOMEM(0xe618002c)#define WUPSMSK2 IOMEM(0xe6180048)#define WUPSFAC IOMEM(0xe6180098)#define IRQCR IOMEM(0xe618022c)#define IRQCR2 IOMEM(0xe6180238)#define IRQCR3 IOMEM(0xe6180244)#define IRQCR4 IOMEM(0xe6180248)#define PDNSEL IOMEM(0xe6180254)/* INTC */#define ICR1A IOMEM(0xe6900000)#define ICR2A IOMEM(0xe6900004)#define ICR3A IOMEM(0xe6900008)#define ICR4A IOMEM(0xe690000c)#define INTMSK00A IOMEM(0xe6900040)#define INTMSK10A IOMEM(0xe6900044)#define INTMSK20A IOMEM(0xe6900048)#define INTMSK30A IOMEM(0xe690004c)/* MFIS *//* FIXME: pointing where? */#define SMFRAM 0xe6a70000/* AP-System Core */#define APARMBAREA IOMEM(0xe6f10020)#ifdef CONFIG_PM#define PM_DOMAIN_ON_OFF_LATENCY_NS	250000static int sh7372_a4r_pd_suspend(void){	sh7372_intcs_suspend();	__raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */	return 0;}static bool a4s_suspend_ready;static int sh7372_a4s_pd_suspend(void){	/*	 * The A4S domain contains the CPU core and therefore it should	 * only be turned off if the CPU is not in use.  This may happen	 * during system suspend, when SYSC is going to be used for generating	 * resume signals and a4s_suspend_ready is set to let	 * sh7372_enter_suspend() know that it can turn A4S off.	 */	a4s_suspend_ready = true;	return -EBUSY;}static void sh7372_a4s_pd_resume(void){	a4s_suspend_ready = false;}static int sh7372_a3sp_pd_suspend(void){	/*	 * Serial consoles make use of SCIF hardware located in A3SP,	 * keep such power domain on if "no_console_suspend" is set.	 */	return console_suspend_enabled ? 0 : -EBUSY;}static struct rmobile_pm_domain sh7372_pm_domains[] = {	{		.genpd.name = "A4LC",		.genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
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