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alarmDataOperation.h

alarmDataOperation.h 6.2 KB
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  1. #ifndef __MACH_MX51_H__
    2. 

  2. #define __MACH_MX51_H__
    3. 

  3. 

  4. /*
    5. 

  5.  * IROM
    6. 

  6.  */
    7. 

  7. #define MX51_IROM_BASE_ADDR		0x0
    8. 

  8. #define MX51_IROM_SIZE			SZ_64K
    9. 

  9. 

  10. /*
    11. 

  11.  * IRAM
    12. 

  12.  */
    13. 

  13. #define MX51_IRAM_BASE_ADDR		0x1ffe0000	/* internal ram */
    14. 

  14. #define MX51_IRAM_PARTITIONS		16
    15. 

  15. #define MX51_IRAM_SIZE		(MX51_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
    16. 

  16. 

  17. #define MX51_GPU_BASE_ADDR		0x20000000
    18. 

  18. #define MX51_GPU_CTRL_BASE_ADDR		0x30000000
    19. 

  19. #define MX51_IPU_CTRL_BASE_ADDR		0x40000000
    20. 

  20. 

  21. /*
    22. 

  22.  * SPBA global module enabled #0
    23. 

  23.  */
    24. 

  24. #define MX51_SPBA0_BASE_ADDR		0x70000000
    25. 

  25. #define MX51_SPBA0_SIZE			SZ_1M
    26. 

  26. 

  27. #define MX51_ESDHC1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x04000)
    28. 

  28. #define MX51_ESDHC2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x08000)
    29. 

  29. #define MX51_UART3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x0c000)
    30. 

  30. #define MX51_ECSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
    31. 

  31. #define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x14000)
    32. 

  32. #define MX51_ESDHC3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x20000)
    33. 

  33. #define MX51_ESDHC4_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x24000)
    34. 

  34. #define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x28000)
    35. 

  35. #define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x30000)
    36. 

  36. #define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x34000)
    37. 

  37. #define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x38000)
    38. 

  38. #define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x3c000)
    39. 

  39. 

  40. /*
    41. 

  41.  * AIPS 1
    42. 

  42.  */
    43. 

  43. #define MX51_AIPS1_BASE_ADDR		0x73f00000
    44. 

  44. #define MX51_AIPS1_SIZE			SZ_1M
    45. 

  45. 

  46. #define MX51_USB_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x80000)
    47. 

  47. #define MX51_USB_OTG_BASE_ADDR		(MX51_USB_BASE_ADDR + 0x0000)
    48. 

  48. #define MX51_USB_HS1_BASE_ADDR		(MX51_USB_BASE_ADDR + 0x0200)
    49. 

  49. #define MX51_USB_HS2_BASE_ADDR		(MX51_USB_BASE_ADDR + 0x0400)
    50. 

  50. #define MX51_GPIO1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x84000)
    51. 

  51. #define MX51_GPIO2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x88000)
    52. 

  52. #define MX51_GPIO3_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x8c000)
    53. 

  53. #define MX51_GPIO4_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x90000)
    54. 

  54. #define MX51_KPP_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x94000)
    55. 

  55. #define MX51_WDOG1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x98000)
    56. 

  56. #define MX51_WDOG2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x9c000)
    57. 

  57. #define MX51_GPT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa0000)
    58. 

  58. #define MX51_SRTC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa4000)
    59. 

  59. #define MX51_IOMUXC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa8000)
    60. 

  60. #define MX51_EPIT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xac000)
    61. 

  61. #define MX51_EPIT2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb0000)
    62. 

  62. #define MX51_PWM1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb4000)
    63. 

  63. #define MX51_PWM2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb8000)
    64. 

  64. #define MX51_UART1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xbc000)
    65. 

  65. #define MX51_UART2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xc0000)
    66. 

  66. #define MX51_SRC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd0000)
    67. 

  67. #define MX51_CCM_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd4000)
    68. 

  68. #define MX51_GPC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd8000)
    69. 

  69. 

  70. /*
    71. 

  71.  * AIPS 2
    72. 

  72.  */
    73. 

  73. #define MX51_AIPS2_BASE_ADDR		0x83f00000
    74. 

  74. #define MX51_AIPS2_SIZE			SZ_1M
    75. 

  75. 

  76. #define MX51_PLL1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x80000)
    77. 

  77. #define MX51_PLL2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x84000)
    78. 

  78. #define MX51_PLL3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x88000)
    79. 

  79. #define MX51_AHBMAX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x94000)
    80. 

  80. #define MX51_IIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x98000)
    81. 

  81. #define MX51_CSU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x9c000)
    82. 

  82. #define MX51_ARM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa0000)
    83. 

  83. #define MX51_OWIRE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa4000)
    84. 

  84. #define MX51_FIRI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa8000)
    85. 

  85. #define MX51_ECSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
    86. 

  86. #define MX51_SDMA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb0000)
    87. 

  87. #define MX51_SCC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb4000)
    88. 

  88. #define MX51_ROMCP_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb8000)
    89. 

  89. #define MX51_RTIC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xbc000)
    90. 

  90. #define MX51_CSPI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
    91. 

  91. #define MX51_I2C2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc4000)
    92. 

  92. #define MX51_I2C1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc8000)
    93. 

  93. #define MX51_SSI1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xcc000)
    94. 

  94. #define MX51_AUDMUX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd0000)
    95. 

  95. #define MX51_M4IF_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd8000)
    96. 

  96. #define MX51_ESDCTL_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd9000)
    97. 

  97. #define MX51_WEIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xda000)
    98. 

  98. #define MX51_NFC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdb000)
    99. 

  99. #define MX51_EMI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdbf00)
    100. 

  100. #define MX51_MIPI_HSC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdc000)
    101. 

  101. #define MX51_ATA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe0000)
    102. 

  102. #define MX51_SIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe4000)
    103. 

  103. #define MX51_SSI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe8000)
    104. 

  104. #define MX51_FEC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xec000)
    105. 

  105. #define MX51_TVE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf0000)
    106. 

  106. #define MX51_VPU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf4000)
    107. 

  107. #define MX51_SAHARA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf8000)
    108. 

  108. 

  109. #define MX51_CSD0_BASE_ADDR		0x90000000
    110. 

  110. #define MX51_CSD1_BASE_ADDR		0xa0000000
    111. 

  111. #define MX51_CS0_BASE_ADDR		0xb0000000
    112. 

  112. #define MX51_CS1_BASE_ADDR		0xb8000000
    113. 

  113. #define MX51_CS2_BASE_ADDR		0xc0000000
    114. 

  114. #define MX51_CS3_BASE_ADDR		0xc8000000
    115. 

  115. #define MX51_CS4_BASE_ADDR		0xcc000000
    116. 

  116. #define MX51_CS5_BASE_ADDR		0xce000000
    117. 

  117. 

  118. /*
    119. 

  119.  * NFC
    120. 

  120.  */
    121. 

  121. #define MX51_NFC_AXI_BASE_ADDR		0xcfff0000	/* NAND flash AXI */
    122. 

  122. #define MX51_NFC_AXI_SIZE		SZ_64K
    123. 

  123. 

  124. #define MX51_GPU2D_BASE_ADDR		0xd0000000
    125. 

  125. #define MX51_TZIC_BASE_ADDR		0xe0000000
    126. 

  126. #define MX51_TZIC_SIZE			SZ_16K
    127. 

  127. 

  128. #define MX51_IO_P2V(x)			IMX_IO_P2V(x)
    129. 

  129. #define MX51_IO_ADDRESS(x)		IOMEM(MX51_IO_P2V(x))
    130. 

  130. 

  131. /*
    132. 

  132.  * defines for SPBA modules
    133. 

  133.  */
    134. 

  134. #define MX51_SPBA_SDHC1	0x04
    135. 

  135. #define MX51_SPBA_SDHC2	0x08
    136. 

  136. #define MX51_SPBA_UART3	0x0c
    137. 

  137. #define MX51_SPBA_CSPI1	0x10
    138. 

  138. #define MX51_SPBA_SSI2	0x14
    139. 

  139. #define MX51_SPBA_SDHC3	0x20
    140. 

  140. #define MX51_SPBA_SDHC4	0x24
    141. 

  141. #define MX51_SPBA_SPDIF	0x28
    142. 

  142. #define MX51_SPBA_ATA	0x30
    143. 

  143. #define MX51_SPBA_SLIM	0x34
    144. 

  144. #define MX51_SPBA_HSI2C	0x38
    145. 

  145. #define MX51_SPBA_CTRL	0x3c
    146. 

  146. 

  147. /*
    148. 

  148.  * Defines for modules using static and dynamic DMA channels
    149. 

  149.  */
    150. 

  150. #define MX51_MXC_DMA_CHANNEL_IRAM	30
    151. 

  151. #define MX51_MXC_DMA_CHANNEL_SPDIF_TX	MXC_DMA_DYNAMIC_CHANNEL
    152. 

  152. #define MX51_MXC_DMA_CHANNEL_UART1_RX	MXC_DMA_DYNAMIC_CHANNEL
    153. 

  153. #define MX51_MXC_DMA_CHANNEL_UART1_TX	MXC_DMA_DYNAMIC_CHANNEL
    154. 

  154. #define MX51_MXC_DMA_CHANNEL_UART2_RX	MXC_DMA_DYNAMIC_CHANNEL
    155. 

  155. #define MX51_MXC_DMA_CHANNEL_UART2_TX	MXC_DMA_DYNAMIC_CHANNEL
    156.