| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191 | /* * Common header file for Blackfin family of processors * * Copyright 2007-2008 Analog Devices Inc. * * Licensed under the GPL-2 or later. */#ifndef _PORTMUX_H_#define _PORTMUX_H_#define P_IDENT(x)	((x) & 0x1FF)#define P_FUNCT(x)	(((x) & 0x3) << 9)#define P_FUNCT2MUX(x)	(((x) >> 9) & 0x3)#define P_DEFINED	0x8000#define P_UNDEF		0x4000#define P_MAYSHARE	0x2000#define P_DONTCARE	0x1000int peripheral_request(unsigned short per, const char *label);void peripheral_free(unsigned short per);int peripheral_request_list(const unsigned short per[], const char *label);void peripheral_free_list(const unsigned short per[]);#include <asm/gpio.h>#include <mach/portmux.h>#ifndef P_SPORT2_TFS#define P_SPORT2_TFS P_UNDEF#endif#ifndef P_SPORT2_DTSEC#define P_SPORT2_DTSEC P_UNDEF#endif#ifndef P_SPORT2_DTPRI#define P_SPORT2_DTPRI P_UNDEF#endif#ifndef P_SPORT2_TSCLK#define P_SPORT2_TSCLK P_UNDEF#endif#ifndef P_SPORT2_RFS#define P_SPORT2_RFS P_UNDEF#endif#ifndef P_SPORT2_DRSEC#define P_SPORT2_DRSEC P_UNDEF#endif#ifndef P_SPORT2_DRPRI#define P_SPORT2_DRPRI P_UNDEF#endif#ifndef P_SPORT2_RSCLK#define P_SPORT2_RSCLK P_UNDEF#endif#ifndef P_SPORT3_TFS#define P_SPORT3_TFS P_UNDEF#endif#ifndef P_SPORT3_DTSEC#define P_SPORT3_DTSEC P_UNDEF#endif#ifndef P_SPORT3_DTPRI#define P_SPORT3_DTPRI P_UNDEF#endif#ifndef P_SPORT3_TSCLK#define P_SPORT3_TSCLK P_UNDEF#endif#ifndef P_SPORT3_RFS#define P_SPORT3_RFS P_UNDEF#endif#ifndef P_SPORT3_DRSEC#define P_SPORT3_DRSEC P_UNDEF#endif#ifndef P_SPORT3_DRPRI#define P_SPORT3_DRPRI P_UNDEF#endif#ifndef P_SPORT3_RSCLK#define P_SPORT3_RSCLK P_UNDEF#endif#ifndef P_TMR4#define P_TMR4 P_UNDEF#endif#ifndef P_TMR5#define P_TMR5 P_UNDEF#endif#ifndef P_TMR6#define P_TMR6 P_UNDEF#endif#ifndef P_TMR7#define P_TMR7 P_UNDEF#endif#ifndef P_TWI1_SCL#define P_TWI1_SCL P_UNDEF#endif#ifndef P_TWI1_SDA#define P_TWI1_SDA P_UNDEF#endif#ifndef P_UART3_RTS#define P_UART3_RTS P_UNDEF#endif#ifndef P_UART3_CTS#define P_UART3_CTS P_UNDEF#endif#ifndef P_UART2_TX#define P_UART2_TX P_UNDEF#endif#ifndef P_UART2_RX#define P_UART2_RX P_UNDEF#endif#ifndef P_UART3_TX#define P_UART3_TX P_UNDEF#endif#ifndef P_UART3_RX#define P_UART3_RX P_UNDEF#endif#ifndef P_SPI2_SS#define P_SPI2_SS P_UNDEF#endif#ifndef P_SPI2_SSEL1#define P_SPI2_SSEL1 P_UNDEF#endif#ifndef P_SPI2_SSEL2#define P_SPI2_SSEL2 P_UNDEF#endif#ifndef P_SPI2_SSEL3#define P_SPI2_SSEL3 P_UNDEF#endif#ifndef P_SPI2_SSEL4#define P_SPI2_SSEL4 P_UNDEF#endif#ifndef P_SPI2_SSEL5#define P_SPI2_SSEL5 P_UNDEF#endif#ifndef P_SPI2_SSEL6#define P_SPI2_SSEL6 P_UNDEF#endif#ifndef P_SPI2_SSEL7#define P_SPI2_SSEL7 P_UNDEF#endif#ifndef P_SPI2_SCK#define P_SPI2_SCK P_UNDEF#endif#ifndef P_SPI2_MOSI#define P_SPI2_MOSI P_UNDEF#endif#ifndef P_SPI2_MISO#define P_SPI2_MISO P_UNDEF#endif#ifndef P_TMR0#define P_TMR0 P_UNDEF#endif#ifndef P_TMR1#define P_TMR1 P_UNDEF#endif#ifndef P_TMR2#define P_TMR2 P_UNDEF#endif#ifndef P_TMR3#define P_TMR3 P_UNDEF#endif#ifndef P_SPORT0_TFS#define P_SPORT0_TFS P_UNDEF#endif#ifndef P_SPORT0_DTSEC#define P_SPORT0_DTSEC P_UNDEF#endif#ifndef P_SPORT0_DTPRI#define P_SPORT0_DTPRI P_UNDEF#endif#ifndef P_SPORT0_TSCLK#define P_SPORT0_TSCLK P_UNDEF#endif#ifndef P_SPORT0_RFS#define P_SPORT0_RFS P_UNDEF#endif#ifndef P_SPORT0_DRSEC#define P_SPORT0_DRSEC P_UNDEF#endif#ifndef P_SPORT0_DRPRI#define P_SPORT0_DRPRI P_UNDEF#endif#ifndef P_SPORT0_RSCLK#define P_SPORT0_RSCLK P_UNDEF#endif#ifndef P_SD_D0#define P_SD_D0 P_UNDEF#endif#ifndef P_SD_D1#define P_SD_D1 P_UNDEF#endif#ifndef P_SD_D2#define P_SD_D2 P_UNDEF#endif#ifndef P_SD_D3#define P_SD_D3 P_UNDEF#endif#ifndef P_SD_CLK#define P_SD_CLK P_UNDEF#endif#ifndef P_SD_CMD#define P_SD_CMD P_UNDEF#endif#ifndef P_MMCLK#define P_MMCLK P_UNDEF#endif#ifndef P_MBCLK#define P_MBCLK P_UNDEF#endif#ifndef P_PPI1_D0#define P_PPI1_D0 P_UNDEF#endif#ifndef P_PPI1_D1#define P_PPI1_D1 P_UNDEF#endif#ifndef P_PPI1_D2#define P_PPI1_D2 P_UNDEF#endif#ifndef P_PPI1_D3#define P_PPI1_D3 P_UNDEF#endif#ifndef P_PPI1_D4#define P_PPI1_D4 P_UNDEF#endif#ifndef P_PPI1_D5#define P_PPI1_D5 P_UNDEF#endif#ifndef P_PPI1_D6#define P_PPI1_D6 P_UNDEF#endif#ifndef P_PPI1_D7#define P_PPI1_D7 P_UNDEF#endif#ifndef P_PPI1_D8#define P_PPI1_D8 P_UNDEF#endif#ifndef P_PPI1_D9#define P_PPI1_D9 P_UNDEF#endif#ifndef P_PPI1_D10#define P_PPI1_D10 P_UNDEF#endif#ifndef P_PPI1_D11#define P_PPI1_D11 P_UNDEF#endif#ifndef P_PPI1_D12#define P_PPI1_D12 P_UNDEF#endif#ifndef P_PPI1_D13#define P_PPI1_D13 P_UNDEF#endif#ifndef P_PPI1_D14#define P_PPI1_D14 P_UNDEF#endif#ifndef P_PPI1_D15#define P_PPI1_D15 P_UNDEF#endif#ifndef P_HOST_D8#define P_HOST_D8 P_UNDEF#endif#ifndef P_HOST_D9#define P_HOST_D9 P_UNDEF#endif#ifndef P_HOST_D10#define P_HOST_D10 P_UNDEF#endif#ifndef P_HOST_D11#define P_HOST_D11 P_UNDEF#endif#ifndef P_HOST_D12#define P_HOST_D12 P_UNDEF#endif#ifndef P_HOST_D13#define P_HOST_D13 P_UNDEF#endif#ifndef P_HOST_D14#define P_HOST_D14 P_UNDEF#endif#ifndef P_HOST_D15#define P_HOST_D15 P_UNDEF#endif#ifndef P_HOST_D0#define P_HOST_D0 P_UNDEF#endif#ifndef P_HOST_D1#define P_HOST_D1 P_UNDEF#endif#ifndef P_HOST_D2#define P_HOST_D2 P_UNDEF#endif#ifndef P_HOST_D3#define P_HOST_D3 P_UNDEF#endif#ifndef P_HOST_D4#define P_HOST_D4 P_UNDEF#endif#ifndef P_HOST_D5#define P_HOST_D5 P_UNDEF#endif#ifndef P_HOST_D6#define P_HOST_D6 P_UNDEF#endif#ifndef P_HOST_D7#define P_HOST_D7 P_UNDEF#endif#ifndef P_SPORT1_TFS#define P_SPORT1_TFS P_UNDEF#endif#ifndef P_SPORT1_DTSEC#define P_SPORT1_DTSEC P_UNDEF#endif#ifndef P_SPORT1_DTPRI#define P_SPORT1_DTPRI P_UNDEF#endif#ifndef P_SPORT1_TSCLK#define P_SPORT1_TSCLK P_UNDEF#endif#ifndef P_SPORT1_RFS#define P_SPORT1_RFS P_UNDEF#endif#ifndef P_SPORT1_DRSEC#define P_SPORT1_DRSEC P_UNDEF#endif#ifndef P_SPORT1_DRPRI#define P_SPORT1_DRPRI P_UNDEF#endif#ifndef P_SPORT1_RSCLK#define P_SPORT1_RSCLK P_UNDEF#endif#ifndef P_PPI2_D0#define P_PPI2_D0 P_UNDEF#endif#ifndef P_PPI2_D1#define P_PPI2_D1 P_UNDEF#endif#ifndef P_PPI2_D2#define P_PPI2_D2 P_UNDEF#endif#ifndef P_PPI2_D3#define P_PPI2_D3 P_UNDEF#endif#ifndef P_PPI2_D4#define P_PPI2_D4 P_UNDEF#endif#ifndef P_PPI2_D5#define P_PPI2_D5 P_UNDEF#endif#ifndef P_PPI2_D6#define P_PPI2_D6 P_UNDEF#endif#ifndef P_PPI2_D7#define P_PPI2_D7 P_UNDEF#endif#ifndef P_PPI0_D18#define P_PPI0_D18 P_UNDEF#endif#ifndef P_PPI0_D19#define P_PPI0_D19 P_UNDEF#endif#ifndef P_PPI0_D20#define P_PPI0_D20 P_UNDEF#endif#ifndef P_PPI0_D21#define P_PPI0_D21 P_UNDEF#endif#ifndef P_PPI0_D22#define P_PPI0_D22 P_UNDEF#endif#ifndef P_PPI0_D23#define P_PPI0_D23 P_UNDEF#endif#ifndef P_KEY_ROW0#define P_KEY_ROW0 P_UNDEF#endif#ifndef P_KEY_ROW1#define P_KEY_ROW1 P_UNDEF#endif#ifndef P_KEY_ROW2#define P_KEY_ROW2 P_UNDEF#endif#ifndef P_KEY_ROW3#define P_KEY_ROW3 P_UNDEF#endif#ifndef P_KEY_COL0#define P_KEY_COL0 P_UNDEF#endif#ifndef P_KEY_COL1#define P_KEY_COL1 P_UNDEF#endif#ifndef P_KEY_COL2#define P_KEY_COL2 P_UNDEF#endif#ifndef P_KEY_COL3#define P_KEY_COL3 P_UNDEF#endif#ifndef P_SPI0_SCK#define P_SPI0_SCK P_UNDEF#endif#ifndef P_SPI0_MISO#define P_SPI0_MISO P_UNDEF#endif#ifndef P_SPI0_MOSI#define P_SPI0_MOSI P_UNDEF#endif#ifndef P_SPI0_SS#define P_SPI0_SS P_UNDEF#endif#ifndef P_SPI0_SSEL1#define P_SPI0_SSEL1 P_UNDEF#endif#ifndef P_SPI0_SSEL2#define P_SPI0_SSEL2 P_UNDEF#endif#ifndef P_SPI0_SSEL3#define P_SPI0_SSEL3 P_UNDEF#endif#ifndef P_SPI0_SSEL4#define P_SPI0_SSEL4 P_UNDEF#endif#ifndef P_SPI0_SSEL5#define P_SPI0_SSEL5 P_UNDEF#endif#ifndef P_SPI0_SSEL6#define P_SPI0_SSEL6 P_UNDEF#endif#ifndef P_SPI0_SSEL7#define P_SPI0_SSEL7 P_UNDEF#endif#ifndef P_UART0_TX#define P_UART0_TX P_UNDEF#endif#ifndef P_UART0_RX#define P_UART0_RX P_UNDEF#endif#ifndef P_UART1_RTS#define P_UART1_RTS P_UNDEF#endif#ifndef P_UART1_CTS#define P_UART1_CTS P_UNDEF#endif#ifndef P_PPI1_CLK#define P_PPI1_CLK P_UNDEF#endif#ifndef P_PPI1_FS1#define P_PPI1_FS1 P_UNDEF#endif#ifndef P_PPI1_FS2#define P_PPI1_FS2 P_UNDEF#endif#ifndef P_TWI0_SCL#define P_TWI0_SCL P_UNDEF#endif#ifndef P_TWI0_SDA#define P_TWI0_SDA P_UNDEF#endif#ifndef P_KEY_COL7#define P_KEY_COL7 P_UNDEF#endif#ifndef P_KEY_ROW6#define P_KEY_ROW6 P_UNDEF#endif#ifndef P_KEY_COL6#define P_KEY_COL6 P_UNDEF#endif#ifndef P_KEY_ROW5#define P_KEY_ROW5 P_UNDEF#endif#ifndef P_KEY_COL5#define P_KEY_COL5 P_UNDEF#endif#ifndef P_KEY_ROW4#define P_KEY_ROW4 P_UNDEF#endif#ifndef P_KEY_COL4#define P_KEY_COL4 P_UNDEF#endif#ifndef P_KEY_ROW7#define P_KEY_ROW7 P_UNDEF#endif#ifndef P_PPI0_D0#define P_PPI0_D0 P_UNDEF#endif#ifndef P_PPI0_D1#define P_PPI0_D1 P_UNDEF#endif#ifndef P_PPI0_D2#define P_PPI0_D2 P_UNDEF#endif#ifndef P_PPI0_D3#define P_PPI0_D3 P_UNDEF#endif#ifndef P_PPI0_D4#define P_PPI0_D4 P_UNDEF#endif#ifndef P_PPI0_D5#define P_PPI0_D5 P_UNDEF#endif#ifndef P_PPI0_D6#define P_PPI0_D6 P_UNDEF#endif#ifndef P_PPI0_D7#define P_PPI0_D7 P_UNDEF#endif#ifndef P_PPI0_D8#define P_PPI0_D8 P_UNDEF#endif#ifndef P_PPI0_D9#define P_PPI0_D9 P_UNDEF#endif#ifndef P_PPI0_D10#define P_PPI0_D10 P_UNDEF#endif#ifndef P_PPI0_D11#define P_PPI0_D11 P_UNDEF#endif#ifndef P_PPI0_D12#define P_PPI0_D12 P_UNDEF#endif#ifndef P_PPI0_D13#define P_PPI0_D13 P_UNDEF#endif#ifndef P_PPI0_D14#define P_PPI0_D14 P_UNDEF#endif#ifndef P_PPI0_D15#define P_PPI0_D15 P_UNDEF#endif#ifndef P_ATAPI_D0A#define P_ATAPI_D0A P_UNDEF#endif#ifndef P_ATAPI_D1A#define P_ATAPI_D1A P_UNDEF#endif#ifndef P_ATAPI_D2A#define P_ATAPI_D2A P_UNDEF#endif#ifndef P_ATAPI_D3A#define P_ATAPI_D3A P_UNDEF#endif#ifndef P_ATAPI_D4A#define P_ATAPI_D4A P_UNDEF#endif#ifndef P_ATAPI_D5A#define P_ATAPI_D5A P_UNDEF#endif#ifndef P_ATAPI_D6A#define P_ATAPI_D6A P_UNDEF#endif#ifndef P_ATAPI_D7A#define P_ATAPI_D7A P_UNDEF#endif#ifndef P_ATAPI_D8A#define P_ATAPI_D8A P_UNDEF#endif#ifndef P_ATAPI_D9A#define P_ATAPI_D9A P_UNDEF#endif#ifndef P_ATAPI_D10A#define P_ATAPI_D10A P_UNDEF#endif#ifndef P_ATAPI_D11A#define P_ATAPI_D11A P_UNDEF#endif#ifndef P_ATAPI_D12A#define P_ATAPI_D12A P_UNDEF#endif#ifndef P_ATAPI_D13A#define P_ATAPI_D13A P_UNDEF#endif#ifndef P_ATAPI_D14A#define P_ATAPI_D14A P_UNDEF#endif#ifndef P_ATAPI_D15A#define P_ATAPI_D15A P_UNDEF#endif#ifndef P_PPI0_CLK#define P_PPI0_CLK P_UNDEF#endif#ifndef P_PPI0_FS1#define P_PPI0_FS1 P_UNDEF#endif#ifndef P_PPI0_FS2#define P_PPI0_FS2 P_UNDEF#endif#ifndef P_PPI0_D16#define P_PPI0_D16 P_UNDEF#endif#ifndef P_PPI0_D17#define P_PPI0_D17 P_UNDEF#endif#ifndef P_SPI1_SSEL1#define P_SPI1_SSEL1 P_UNDEF#endif#ifndef P_SPI1_SSEL2#define P_SPI1_SSEL2 P_UNDEF#endif#ifndef P_SPI1_SSEL3#define P_SPI1_SSEL3 P_UNDEF#endif#ifndef P_SPI1_SSEL4#define P_SPI1_SSEL4 P_UNDEF#endif#ifndef P_SPI1_SSEL5#define P_SPI1_SSEL5 P_UNDEF#endif#ifndef P_SPI1_SSEL6#define P_SPI1_SSEL6 P_UNDEF#endif#ifndef P_SPI1_SSEL7#define P_SPI1_SSEL7 P_UNDEF#endif#ifndef P_SPI1_SCK#define P_SPI1_SCK P_UNDEF#endif#ifndef P_SPI1_MISO#define P_SPI1_MISO P_UNDEF#endif#ifndef P_SPI1_MOSI#define P_SPI1_MOSI P_UNDEF#endif#ifndef P_SPI1_SS#define P_SPI1_SS P_UNDEF#endif#ifndef P_CAN0_TX#define P_CAN0_TX P_UNDEF#endif#ifndef P_CAN0_RX#define P_CAN0_RX P_UNDEF#endif#ifndef P_CAN1_TX#define P_CAN1_TX P_UNDEF#endif#ifndef P_CAN1_RX#define P_CAN1_RX P_UNDEF#endif#ifndef P_ATAPI_A0A#define P_ATAPI_A0A P_UNDEF#endif#ifndef P_ATAPI_A1A#define P_ATAPI_A1A P_UNDEF#endif#ifndef P_ATAPI_A2A#define P_ATAPI_A2A P_UNDEF#endif#ifndef P_HOST_CE#define P_HOST_CE P_UNDEF#endif#ifndef P_HOST_RD#define P_HOST_RD P_UNDEF#endif#ifndef P_HOST_WR#define P_HOST_WR P_UNDEF#endif#ifndef P_MTXONB#define P_MTXONB P_UNDEF#endif#ifndef P_PPI2_FS2#define P_PPI2_FS2 P_UNDEF#endif#ifndef P_PPI2_FS1#define P_PPI2_FS1 P_UNDEF#endif#ifndef P_PPI2_CLK#define P_PPI2_CLK P_UNDEF#endif#ifndef P_CNT_CZM#define P_CNT_CZM P_UNDEF#endif#ifndef P_UART1_TX#define P_UART1_TX P_UNDEF#endif#ifndef P_UART1_RX#define P_UART1_RX P_UNDEF#endif#ifndef P_ATAPI_RESET#define P_ATAPI_RESET P_UNDEF#endif#ifndef P_HOST_ADDR#define P_HOST_ADDR P_UNDEF#endif#ifndef P_HOST_ACK#define P_HOST_ACK P_UNDEF#endif#ifndef P_MTX#define P_MTX P_UNDEF#endif#ifndef P_MRX#define P_MRX P_UNDEF#endif#ifndef P_MRXONB#define P_MRXONB P_UNDEF#endif#ifndef P_A4#define P_A4 P_UNDEF#endif#ifndef P_A5#define P_A5 P_UNDEF#endif#ifndef P_A6#define P_A6 P_UNDEF#endif#ifndef P_A7#define P_A7 P_UNDEF#endif#ifndef P_A8#define P_A8 P_UNDEF#endif#ifndef P_A9#define P_A9 P_UNDEF#endif#ifndef P_PPI1_FS3#define P_PPI1_FS3 P_UNDEF#endif#ifndef P_PPI2_FS3#define P_PPI2_FS3 P_UNDEF#endif#ifndef P_TMR8#define P_TMR8 P_UNDEF#endif#ifndef P_TMR9#define P_TMR9 P_UNDEF#endif#ifndef P_TMR10#define P_TMR10 P_UNDEF#endif#ifndef P_TMR11#define P_TMR11 P_UNDEF#endif#ifndef P_DMAR0#define P_DMAR0 P_UNDEF#endif#ifndef P_DMAR1#define P_DMAR1 P_UNDEF#endif#ifndef P_PPI0_FS3#define P_PPI0_FS3 P_UNDEF#endif#ifndef P_CNT_CDG#define P_CNT_CDG P_UNDEF#endif#ifndef P_CNT_CUD#define P_CNT_CUD P_UNDEF#endif#ifndef P_A10#define P_A10 P_UNDEF#endif#ifndef P_A11#define P_A11 P_UNDEF#endif#ifndef P_A12#define P_A12 P_UNDEF#endif#ifndef P_A13#define P_A13 P_UNDEF#endif#ifndef P_A14#define P_A14 P_UNDEF#endif#ifndef P_A15#define P_A15 P_UNDEF#endif#ifndef P_A16#define P_A16 P_UNDEF#endif#ifndef P_A17#define P_A17 P_UNDEF#endif#ifndef P_A18#define P_A18 P_UNDEF#endif#ifndef P_A19#define P_A19 P_UNDEF#endif#ifndef P_A20#define P_A20 P_UNDEF#endif#ifndef P_A21#define P_A21 P_UNDEF#endif#ifndef P_A22#define P_A22 P_UNDEF#endif#ifndef P_A23#define P_A23 P_UNDEF#endif#ifndef P_A24#define P_A24 P_UNDEF#endif#ifndef P_A25#define P_A25 P_UNDEF#endif#ifndef P_NOR_CLK#define P_NOR_CLK P_UNDEF#endif#ifndef P_TMRCLK#define P_TMRCLK P_UNDEF#endif#ifndef P_AMC_ARDY_NOR_WAIT#define P_AMC_ARDY_NOR_WAIT P_UNDEF#endif#ifndef P_NAND_CE#define P_NAND_CE P_UNDEF#endif#ifndef P_NAND_RB#define P_NAND_RB P_UNDEF#endif#ifndef P_ATAPI_DIOR#define P_ATAPI_DIOR P_UNDEF#endif#ifndef P_ATAPI_DIOW#define P_ATAPI_DIOW P_UNDEF#endif#ifndef P_ATAPI_CS0#define P_ATAPI_CS0 P_UNDEF#endif#ifndef P_ATAPI_CS1#define P_ATAPI_CS1 P_UNDEF#endif#ifndef P_ATAPI_DMACK#define P_ATAPI_DMACK P_UNDEF#endif#ifndef P_ATAPI_DMARQ#define P_ATAPI_DMARQ P_UNDEF#endif#ifndef P_ATAPI_INTRQ#define P_ATAPI_INTRQ P_UNDEF#endif#ifndef P_ATAPI_IORDY#define P_ATAPI_IORDY P_UNDEF#endif#ifndef P_AMC_BR#define P_AMC_BR P_UNDEF#endif#ifndef P_AMC_BG#define P_AMC_BG P_UNDEF#endif#ifndef P_AMC_BGH#define P_AMC_BGH P_UNDEF#endif/* EMAC */#ifndef P_MII0_ETxD0#define P_MII0_ETxD0 P_UNDEF#endif#ifndef P_MII0_ETxD1#define P_MII0_ETxD1 P_UNDEF#endif#ifndef P_MII0_ETxD2#define P_MII0_ETxD2 P_UNDEF#endif#ifndef P_MII0_ETxD3#define P_MII0_ETxD3 P_UNDEF#endif#ifndef P_MII0_ETxEN#define P_MII0_ETxEN P_UNDEF#endif#ifndef P_MII0_TxCLK#define P_MII0_TxCLK P_UNDEF#endif#ifndef P_MII0_PHYINT#define P_MII0_PHYINT P_UNDEF#endif#ifndef P_MII0_COL#define P_MII0_COL P_UNDEF#endif#ifndef P_MII0_ERxD0#define P_MII0_ERxD0 P_UNDEF#endif#ifndef P_MII0_ERxD1#define P_MII0_ERxD1 P_UNDEF#endif#ifndef P_MII0_ERxD2#define P_MII0_ERxD2 P_UNDEF#endif#ifndef P_MII0_ERxD3#define P_MII0_ERxD3 P_UNDEF#endif#ifndef P_MII0_ERxDV#define P_MII0_ERxDV P_UNDEF#endif#ifndef P_MII0_ERxCLK#define P_MII0_ERxCLK P_UNDEF#endif#ifndef P_MII0_ERxER#define P_MII0_ERxER P_UNDEF#endif#ifndef P_MII0_CRS#define P_MII0_CRS P_UNDEF#endif#ifndef P_RMII0_REF_CLK#define P_RMII0_REF_CLK P_UNDEF#endif#ifndef P_RMII0_MDINT#define P_RMII0_MDINT P_UNDEF#endif#ifndef P_RMII0_CRS_DV#define P_RMII0_CRS_DV P_UNDEF#endif#ifndef P_MDC#define P_MDC P_UNDEF#endif#ifndef P_MDIO#define P_MDIO P_UNDEF#endif#endif				/* _PORTMUX_H_ */
 |