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functionDefinition.h

functionDefinition.h 60 KB
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  1. /*
    2. 

  2.  * Copyright 2005-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF534_H
    8. 

  8. #define _DEF_BF534_H
    9. 

  9. 

  10. /************************************************************************************
    11. 

  11. ** System MMR Register Map
    12. 

  12. *************************************************************************************/
    13. 

  13. /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
    14. 

  14. #define PLL_CTL				0xFFC00000	/* PLL Control Register                                         */
    15. 

  15. #define PLL_DIV				0xFFC00004	/* PLL Divide Register                                          */
    16. 

  16. #define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register           */
    17. 

  17. #define PLL_STAT			0xFFC0000C	/* PLL Status Register                                          */
    18. 

  18. #define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register                                      */
    19. 

  19. #define CHIPID				0xFFC00014      /* Chip ID Register                                             */
    20. 

  20. 

  21. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
    22. 

  22. #define SWRST				0xFFC00100	/* Software Reset Register                                      */
    23. 

  23. #define SYSCR				0xFFC00104	/* System Configuration Register                        */
    24. 

  24. #define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register      */
    25. 

  25. #define SIC_IMASK			0xFFC0010C	/* Interrupt Mask Register                                      */
    26. 

  26. #define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0                      */
    27. 

  27. #define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1                      */
    28. 

  28. #define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2                      */
    29. 

  29. #define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3                      */
    30. 

  30. #define SIC_ISR				0xFFC00120	/* Interrupt Status Register                            */
    31. 

  31. #define SIC_IWR				0xFFC00124	/* Interrupt Wakeup Register                            */
    32. 

  32. 

  33. /* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
    34. 

  34. #define WDOG_CTL			0xFFC00200	/* Watchdog Control Register                            */
    35. 

  35. #define WDOG_CNT			0xFFC00204	/* Watchdog Count Register                                      */
    36. 

  36. #define WDOG_STAT			0xFFC00208	/* Watchdog Status Register                                     */
    37. 

  37. 

  38. /* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
    39. 

  39. #define RTC_STAT			0xFFC00300	/* RTC Status Register                                          */
    40. 

  40. #define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register                       */
    41. 

  41. #define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register                        */
    42. 

  42. #define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register                         */
    43. 

  43. #define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register                                      */
    44. 

  44. #define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register                        */
    45. 

  45. #define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro         */
    46. 

  46. 

  47. /* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
    48. 

  48. #define UART0_THR			0xFFC00400	/* Transmit Holding register                            */
    49. 

  49. #define UART0_RBR			0xFFC00400	/* Receive Buffer register                                      */
    50. 

  50. #define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)                                     */
    51. 

  51. #define UART0_IER			0xFFC00404	/* Interrupt Enable Register                            */
    52. 

  52. #define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)                            */
    53. 

  53. #define UART0_IIR			0xFFC00408	/* Interrupt Identification Register            */
    54. 

  54. #define UART0_LCR			0xFFC0040C	/* Line Control Register                                        */
    55. 

  55. #define UART0_MCR			0xFFC00410	/* Modem Control Register                                       */
    56. 

  56. #define UART0_LSR			0xFFC00414	/* Line Status Register                                         */
    57. 

  57. #define UART0_MSR			0xFFC00418	/* Modem Status Register                                        */
    58. 

  58. #define UART0_SCR			0xFFC0041C	/* SCR Scratch Register                                         */
    59. 

  59. #define UART0_GCTL			0xFFC00424	/* Global Control Register                                      */
    60. 

  60. 

  61. /* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/
    62. 

  62. #define SPI0_REGBASE			0xFFC00500
    63. 

  63. #define SPI_CTL				0xFFC00500	/* SPI Control Register                                         */
    64. 

  64. #define SPI_FLG				0xFFC00504	/* SPI Flag register                                            */
    65. 

  65. #define SPI_STAT			0xFFC00508	/* SPI Status register                                          */
    66. 

  66. #define SPI_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register            */
    67. 

  67. #define SPI_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register                     */
    68. 

  68. #define SPI_BAUD			0xFFC00514	/* SPI Baud rate Register                                       */
    69. 

  69. #define SPI_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register                                     */
    70. 

  70. 

  71. /* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
    72. 

  72. #define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register                       */
    73. 

  73. #define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register                                     */
    74. 

  74. #define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register                                      */
    75. 

  75. #define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register                                       */
    76. 

  76. 

  77. #define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register                       */
    78. 

  78. #define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register                             */
    79. 

  79. #define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register                              */
    80. 

  80. #define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register                               */
    81. 

  81. 

  82. #define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register                       */
    83. 

  83. #define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register                             */
    84. 

  84. #define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register                              */
    85. 

  85. #define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register                               */
    86. 

  86. 

  87. #define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register                       */
    88. 

  88. #define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register                                     */
    89. 

  89. #define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register                                      */
    90. 

  90. #define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register                                       */
    91. 

  91. 

  92. #define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register                       */
    93. 

  93. #define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register                             */
    94. 

  94. #define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register                              */
    95. 

  95. #define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register                               */
    96. 

  96. 

  97. #define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register                       */
    98. 

  98. #define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register                             */
    99. 

  99. #define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register                              */
    100. 

  100. #define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register                               */
    101. 

  101. 

  102. #define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register                       */
    103. 

  103. #define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register                             */
    104. 

  104. #define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register                              */
    105. 

  105. #define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register                               */
    106. 

  106. 

  107. #define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register                       */
    108. 

  108. #define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register                             */
    109. 

  109. #define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register                              */
    110. 

  110. #define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register                               */
    111. 

  111. 

  112. #define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register                                        */
    113. 

  113. #define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register                                       */
    114. 

  114. #define TIMER_STATUS		0xFFC00688	/* Timer Status Register                                        */
    115. 

  115. 

  116. /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)												*/
    117. 

  117. #define PORTFIO					0xFFC00700	/* Port F I/O Pin State Specify Register                                */
    118. 

  118. #define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register               */
    119. 

  119. #define PORTFIO_SET				0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register                 */
    120. 

  120. #define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register                                 */
    121. 

  121. #define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register   */
    122. 

  122. #define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register                 */
    123. 

  123. #define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register                  */
    124. 

  124. #define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register   */
    125. 

  125. #define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register   */
    126. 

  126. #define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register                 */
    127. 

  127. #define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register                  */
    128. 

  128. #define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register   */
    129. 

  129. #define PORTFIO_DIR				0xFFC00730	/* Port F I/O Direction Register                                                */
    130. 

  130. #define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register                                  */
    131. 

  131. #define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register                               */
    132. 

  132. #define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register                                */
    133. 

  133. #define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register                                     */
    134. 

  134. 

  135. /* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)										*/
    136. 

  136. #define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register                     */
    137. 

  137. #define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register                     */
    138. 

  138. #define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider                                        */
    139. 

  139. #define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider                           */
    140. 

  140. #define SPORT0_TX			0xFFC00810	/* SPORT0 TX Data Register                                                      */
    141. 

  141. #define SPORT0_RX			0xFFC00818	/* SPORT0 RX Data Register                                                      */
    142. 

  142. #define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register                     */
    143. 

  143. #define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register                     */
    144. 

  144. #define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider                                         */
    145. 

  145. #define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider                            */
    146. 

  146. #define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register                                                       */
    147. 

  147. #define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register                                      */
    148. 

  148. #define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1        */
    149. 

  149. #define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2        */
    150. 

  150. #define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0      */
    151. 

  151. #define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1      */
    152. 

  152. #define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2      */
    153. 

  153. #define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3      */
    154. 

  154. #define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0       */
    155. 

  155. #define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1       */
    156. 

  156. #define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2       */
    157. 

  157. #define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3       */
    158. 

  158. 

  159. /* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)										*/
    160. 

  160. #define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register                     */
    161. 

  161. #define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register                     */
    162. 

  162. #define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider                                        */
    163. 

  163. #define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider                           */
    164. 

  164. #define SPORT1_TX			0xFFC00910	/* SPORT1 TX Data Register                                                      */
    165. 

  165. #define SPORT1_RX			0xFFC00918	/* SPORT1 RX Data Register                                                      */
    166. 

  166. #define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register                     */
    167. 

  167. #define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register                     */
    168. 

  168. #define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider                                         */
    169. 

  169. #define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider                            */
    170. 

  170. #define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register                                                       */
    171. 

  171. #define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register                                      */
    172. 

  172. #define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1        */
    173. 

  173. #define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2        */
    174. 

  174. #define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0      */
    175. 

  175. #define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1      */
    176. 

  176. #define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2      */
    177. 

  177. #define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3      */
    178. 

  178. #define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0       */
    179. 

  179. #define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1       */
    180. 

  180. #define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2       */
    181. 

  181. #define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3       */
    182. 

  182. 

  183. /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)								*/
    184. 

  184. #define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register  */
    185. 

  185. #define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0  */
    186. 

  186. #define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1  */
    187. 

  187. #define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register                                */
    188. 

  188. #define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register                                  */
    189. 

  189. #define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register                  */
    190. 

  190. #define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register                                                */
    191. 

  191. 

  192. /* DMA Traffic Control Registers													*/
    193. 

  193. #define DMAC_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
    194. 

  194. #define DMAC_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
    195. 

  195. 

  196. /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/
    197. 

  197. #define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register               */
    198. 

  198. #define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register                                 */
    199. 

  199. #define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register                                 */
    200. 

  200. #define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register                                               */
    201. 

  201. #define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register                                              */
    202. 

  202. #define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register                                               */
    203. 

  203. #define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register                                              */
    204. 

  204. #define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register    */
    205. 

  205. #define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register                               */
    206. 

  206. #define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register                              */
    207. 

  207. #define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register                                */
    208. 

  208. #define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register                               */
    209. 

  209. #define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register                               */
    210. 

  210. 

  211. #define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register               */
    212. 

  212. #define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register                                 */
    213. 

  213. #define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register                                 */
    214. 

  214. #define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register                                               */
    215. 

  215. #define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register                                              */
    216. 

  216. #define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register                                               */
    217. 

  217. #define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register                                              */
    218. 

  218. #define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register    */
    219. 

  219. #define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register                               */
    220. 

  220. #define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register                              */
    221. 

  221. #define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register                                */
    222. 

  222. #define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register                               */
    223. 

  223. #define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register                               */
    224. 

  224. 

  225. #define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register               */
    226. 

  226. #define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register                                 */
    227. 

  227. #define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register                                 */
    228. 

  228. #define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register                                               */
    229. 

  229. #define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register                                              */
    230. 

  230. #define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register                                               */
    231. 

  231. #define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register                                              */
    232. 

  232. #define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register    */
    233. 

  233. #define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register                               */
    234. 

  234. #define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register                              */
    235. 

  235. #define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register                                */
    236. 

  236. #define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register                               */
    237. 

  237. #define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register                               */
    238. 

  238. 

  239. #define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register               */
    240. 

  240. #define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register                                 */
    241. 

  241. #define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register                                 */
    242. 

  242. #define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register                                               */
    243. 

  243. #define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register                                              */
    244. 

  244. #define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register                                               */
    245. 

  245. #define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register                                              */
    246. 

  246. #define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register    */
    247. 

  247. #define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register                               */
    248. 

  248. #define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register                              */
    249. 

  249. #define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register                                */
    250. 

  250. #define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register                               */
    251. 

  251. #define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register                               */
    252. 

  252. 

  253. #define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register               */
    254. 

  254. #define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register                                 */
    255. 

  255. #define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register                                 */
    256. 

  256. #define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register                                               */
    257. 

  257. #define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register                                              */
    258. 

  258. #define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register                                               */
    259. 

  259. #define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register                                              */
    260. 

  260. #define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register    */
    261. 

  261. #define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register                               */
    262. 

  262. #define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register                              */
    263. 

  263. #define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register                                */
    264. 

  264. #define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register                               */
    265. 

  265. #define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register                               */
    266. 

  266. 

  267. #define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register               */
    268. 

  268. #define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register                                 */
    269. 

  269. #define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register                                 */
    270. 

  270. #define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register                                               */
    271. 

  271. #define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register                                              */
    272. 

  272. #define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register                                               */
    273. 

  273. #define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register                                              */
    274. 

  274. #define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register    */
    275. 

  275. #define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register                               */
    276. 

  276. #define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register                              */
    277. 

  277. #define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register                                */
    278. 

  278. #define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register                               */
    279. 

  279. #define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register                               */
    280. 

  280. 

  281. #define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register               */
    282. 

  282. #define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register                                 */
    283. 

  283. #define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register                                 */
    284. 

  284. #define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register                                               */
    285. 

  285. #define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register                                              */
    286. 

  286. #define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register                                               */
    287. 

  287. #define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register                                              */
    288. 

  288. #define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register    */
    289. 

  289. #define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register                               */
    290. 

  290. #define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register                              */
    291. 

  291. #define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register                                */
    292. 

  292. #define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register                               */
    293. 

  293. #define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register                               */
    294. 

  294. 

  295. #define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register               */
    296. 

  296. #define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register                                 */
    297. 

  297. #define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register                                 */
    298. 

  298. #define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register                                               */
    299. 

  299. #define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register                                              */
    300. 

  300. #define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register                                               */
    301. 

  301. #define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register                                              */
    302. 

  302. #define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register    */
    303. 

  303. #define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register                               */
    304. 

  304. #define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register                              */
    305. 

  305. #define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register                                */
    306. 

  306. #define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register                               */
    307. 

  307. #define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register                               */
    308. 

  308. 

  309. #define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register               */
    310. 

  310. #define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register                                 */
    311. 

  311. #define DMA8_CONFIG				0xFFC00E08	/* DMA Channel 8 Configuration Register                                 */
    312. 

  312. #define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register                                               */
    313. 

  313. #define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register                                              */
    314. 

  314. #define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register                                               */
    315. 

  315. #define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register                                              */
    316. 

  316. #define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register    */
    317. 

  317. #define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register                               */
    318. 

  318. #define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register                              */
    319. 

  319. #define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register                                */
    320. 

  320. #define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register                               */
    321. 

  321. #define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register                               */
    322. 

  322. 

  323. #define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register               */
    324. 

  324. #define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register                                 */
    325. 

  325. #define DMA9_CONFIG				0xFFC00E48	/* DMA Channel 9 Configuration Register                                 */
    326. 

  326. #define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register                                               */
    327. 

  327. #define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register                                              */
    328. 

  328. #define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register                                               */
    329. 

  329. #define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register                                              */
    330. 

  330. #define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register    */
    331. 

  331. #define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register                               */
    332. 

  332. #define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register                              */
    333. 

  333. #define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register                                */
    334. 

  334. #define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register                               */
    335. 

  335. #define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register                               */
    336. 

  336. 

  337. #define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register              */
    338. 

  338. #define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register                                */
    339. 

  339. #define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register                                */
    340. 

  340. #define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register                                              */
    341. 

  341. #define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register                                             */
    342. 

  342. #define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register                                              */
    343. 

  343. #define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register                                             */
    344. 

  344. #define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register   */
    345. 

  345. #define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register                              */
    346. 

  346. #define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register                             */
    347. 

  347. #define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register                               */
    348. 

  348. #define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register                              */
    349. 

  349. #define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register                              */
    350. 

  350. 

  351. #define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register              */
    352. 

  352. #define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register                                */
    353. 

  353. #define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register                                */
    354. 

  354. #define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register                                              */
    355. 

  355. #define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register                                             */
    356. 

  356. #define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register                                              */
    357. 

  357. #define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register                                             */
    358. 

  358. #define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register   */
    359. 

  359. #define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register                              */
    360. 

  360. #define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register                             */
    361. 

  361. #define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register                               */
    362. 

  362. #define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register                              */
    363. 

  363. #define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register                              */
    364. 

  364. 

  365. #define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
    366. 

  366. #define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register                           */
    367. 

  367. #define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register                           */
    368. 

  368. #define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register                                         */
    369. 

  369. #define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register                                        */
    370. 

  370. #define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register                                         */
    371. 

  371. #define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register                                        */
    372. 

  372. #define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
    373. 

  373. #define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register                         */
    374. 

  374. #define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register                        */
    375. 

  375. #define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register                          */
    376. 

  376. #define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register                         */
    377. 

  377. #define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register                         */
    378. 

  378. 

  379. #define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
    380. 

  380. #define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register                                        */
    381. 

  381. #define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register                                        */
    382. 

  382. #define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register                                                      */
    383. 

  383. #define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register                                                     */
    384. 

  384. #define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register                                                      */
    385. 

  385. #define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register                                                     */
    386. 

  386. #define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
    387. 

  387. #define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register                                      */
    388. 

  388. #define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register                                     */
    389. 

  389. #define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register                                       */
    390. 

  390. #define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register                                      */
    391. 

  391. #define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register                                      */
    392. 

  392. 

  393. #define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
    394. 

  394. #define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register                           */
    395. 

  395. #define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register                           */
    396. 

  396. #define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register                                         */
    397. 

  397. #define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register                                        */
    398. 

  398. #define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register                                         */
    399. 

  399. #define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register                                        */
    400. 

  400. #define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
    401. 

  401. #define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register                         */
    402. 

  402. #define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register                        */
    403. 

  403. #define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register                          */
    404. 

  404. #define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register                         */
    405. 

  405. #define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register                         */
    406. 

  406. 

  407. #define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
    408. 

  408. #define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register                                        */
    409. 

  409. #define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register                                        */
    410. 

  410. #define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register                                                      */
    411. 

  411. #define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register                                                     */
    412. 

  412. #define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register                                                      */
    413. 

  413. #define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register                                                     */
    414. 

  414. #define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
    415. 

  415. #define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register                                      */
    416. 

  416. #define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register                                     */
    417. 

  417. #define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register                                       */
    418. 

  418. #define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register                                      */
    419. 

  419. #define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register                                      */
    420. 

  420. 

  421. /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)				*/
    422. 

  422. #define PPI_CONTROL			0xFFC01000	/* PPI Control Register                 */
    423. 

  423. #define PPI_STATUS			0xFFC01004	/* PPI Status Register                  */
    424. 

  424. #define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register  */
    425. 

  425. #define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register             */
    426. 

  426. #define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register    */
    427. 

  427. 

  428. /* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
    429. 

  429. #define TWI0_REGBASE			0xFFC01400
    430. 

  430. #define TWI0_CLKDIV			0xFFC01400	/* Serial Clock Divider Register                        */
    431. 

  431. #define TWI0_CONTROL			0xFFC01404	/* TWI Control Register                                         */
    432. 

  432. #define TWI0_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register                          */
    433. 

  433. #define TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register                           */
    434. 

  434. #define TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register                          */
    435. 

  435. #define TWI0_MASTER_CTL		0xFFC01414	/* Master Mode Control Register                         */
    436. 

  436. #define TWI0_MASTER_STAT		0xFFC01418	/* Master Mode Status Register                          */
    437. 

  437. #define TWI0_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register                         */
    438. 

  438. #define TWI0_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register                        */
    439. 

  439. #define TWI0_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register           */
    440. 

  440. #define TWI0_FIFO_CTL		0xFFC01428	/* FIFO Control Register                                        */
    441. 

  441. #define TWI0_FIFO_STAT		0xFFC0142C	/* FIFO Status Register                                         */
    442. 

  442. #define TWI0_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register      */
    443. 

  443. #define TWI0_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register      */
    444. 

  444. #define TWI0_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register       */
    445. 

  445. #define TWI0_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register       */
    446. 

  446. 

  447. /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)												*/
    448. 

  448. #define PORTGIO					0xFFC01500	/* Port G I/O Pin State Specify Register                                */
    449. 

  449. #define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register               */
    450. 

  450. #define PORTGIO_SET				0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register                 */
    451. 

  451. #define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register                                 */
    452. 

  452. #define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register   */
    453. 

  453. #define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register                 */
    454. 

  454. #define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register                  */
    455. 

  455. #define PORTGIO_MASKA_TOGGLE	0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register   */
    456. 

  456. #define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register   */
    457. 

  457. #define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register                 */
    458. 

  458. #define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register                  */
    459. 

  459. #define PORTGIO_MASKB_TOGGLE	0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register   */
    460. 

  460. #define PORTGIO_DIR				0xFFC01530	/* Port G I/O Direction Register                                                */
    461. 

  461. #define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register                                  */
    462. 

  462. #define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register                               */
    463. 

  463. #define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register                                */
    464. 

  464. #define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register                                             */
    465. 

  465. 

  466. /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)												*/
    467. 

  467. #define PORTHIO					0xFFC01700	/* Port H I/O Pin State Specify Register                                */
    468. 

  468. #define PORTHIO_CLEAR			0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register               */
    469. 

  469. #define PORTHIO_SET				0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register                 */
    470. 

  470. #define PORTHIO_TOGGLE			0xFFC0170C	/* Port H I/O Pin State Toggle Register                                 */
    471. 

  471. #define PORTHIO_MASKA			0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register   */
    472. 

  472. #define PORTHIO_MASKA_CLEAR		0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register                 */
    473. 

  473. #define PORTHIO_MASKA_SET		0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register                  */
    474. 

  474. #define PORTHIO_MASKA_TOGGLE	0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register   */
    475. 

  475. #define PORTHIO_MASKB			0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register   */
    476. 

  476. #define PORTHIO_MASKB_CLEAR		0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register                 */
    477. 

  477. #define PORTHIO_MASKB_SET		0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register                  */
    478. 

  478. #define PORTHIO_MASKB_TOGGLE	0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register   */
    479. 

  479. #define PORTHIO_DIR				0xFFC01730	/* Port H I/O Direction Register                                                */
    480. 

  480. #define PORTHIO_POLAR			0xFFC01734	/* Port H I/O Source Polarity Register                                  */
    481. 

  481. #define PORTHIO_EDGE			0xFFC01738	/* Port H I/O Source Sensitivity Register                               */
    482. 

  482. #define PORTHIO_BOTH			0xFFC0173C	/* Port H I/O Set on BOTH Edges Register                                */
    483. 

  483. #define PORTHIO_INEN			0xFFC01740	/* Port H I/O Input Enable Register                                             */
    484. 

  484. 

  485. /* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
    486. 

  486. #define UART1_THR			0xFFC02000	/* Transmit Holding register                    */
    487. 

  487. #define UART1_RBR			0xFFC02000	/* Receive Buffer register                              */
    488. 

  488. #define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)                             */
    489. 

  489. #define UART1_IER			0xFFC02004	/* Interrupt Enable Register                    */
    490. 

  490. #define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)                    */
    491. 

  491. #define UART1_IIR			0xFFC02008	/* Interrupt Identification Register    */
    492. 

  492. #define UART1_LCR			0xFFC0200C	/* Line Control Register                                */
    493. 

  493. #define UART1_MCR			0xFFC02010	/* Modem Control Register                               */
    494. 

  494. #define UART1_LSR			0xFFC02014	/* Line Status Register                                 */
    495. 

  495. #define UART1_MSR			0xFFC02018	/* Modem Status Register                                */
    496. 

  496. #define UART1_SCR			0xFFC0201C	/* SCR Scratch Register                                 */
    497. 

  497. #define UART1_GCTL			0xFFC02024	/* Global Control Register                              */
    498. 

  498. 

  499. /* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)										*/
    500. 

  500. /* For Mailboxes 0-15																	*/
    501. 

  501. #define CAN_MC1				0xFFC02A00	/* Mailbox config reg 1                                                 */
    502. 

  502. #define CAN_MD1				0xFFC02A04	/* Mailbox direction reg 1                                              */
    503. 

  503. #define CAN_TRS1			0xFFC02A08	/* Transmit Request Set reg 1                                   */
    504. 

  504. #define CAN_TRR1			0xFFC02A0C	/* Transmit Request Reset reg 1                                 */
    505. 

  505. #define CAN_TA1				0xFFC02A10	/* Transmit Acknowledge reg 1                                   */
    506. 

  506. #define CAN_AA1				0xFFC02A14	/* Transmit Abort Acknowledge reg 1                             */
    507. 

  507. #define CAN_RMP1			0xFFC02A18	/* Receive Message Pending reg 1                                */
    508. 

  508. #define CAN_RML1			0xFFC02A1C	/* Receive Message Lost reg 1                                   */
    509. 

  509. #define CAN_MBTIF1			0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1                */
    510. 

  510. #define CAN_MBRIF1			0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1                */
    511. 

  511. #define CAN_MBIM1			0xFFC02A28	/* Mailbox Interrupt Mask reg 1                                 */
    512. 

  512. #define CAN_RFH1			0xFFC02A2C	/* Remote Frame Handling reg 1                                  */
    513. 

  513. #define CAN_OPSS1			0xFFC02A30	/* Overwrite Protection Single Shot Xmit reg 1  */
    514. 

  514. 

  515. /* For Mailboxes 16-31   																*/
    516. 

  516. #define CAN_MC2				0xFFC02A40	/* Mailbox config reg 2                                                 */
    517. 

  517. #define CAN_MD2				0xFFC02A44	/* Mailbox direction reg 2                                              */
    518. 

  518. #define CAN_TRS2			0xFFC02A48	/* Transmit Request Set reg 2                                   */
    519. 

  519. #define CAN_TRR2			0xFFC02A4C	/* Transmit Request Reset reg 2                                 */
    520. 

  520. #define CAN_TA2				0xFFC02A50	/* Transmit Acknowledge reg 2                                   */
    521. 

  521. #define CAN_AA2				0xFFC02A54	/* Transmit Abort Acknowledge reg 2                             */
    522. 

  522. #define CAN_RMP2			0xFFC02A58	/* Receive Message Pending reg 2                                */
    523. 

  523. #define CAN_RML2			0xFFC02A5C	/* Receive Message Lost reg 2                                   */
    524. 

  524. #define CAN_MBTIF2			0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2                */
    525. 

  525. #define CAN_MBRIF2			0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2                */
    526. 

  526. #define CAN_MBIM2			0xFFC02A68	/* Mailbox Interrupt Mask reg 2                                 */
    527. 

  527. #define CAN_RFH2			0xFFC02A6C	/* Remote Frame Handling reg 2                                  */
    528. 

  528. #define CAN_OPSS2			0xFFC02A70	/* Overwrite Protection Single Shot Xmit reg 2  */
    529. 

  529. 

  530. /* CAN Configuration, Control, and Status Registers										*/
    531. 

  531. #define CAN_CLOCK			0xFFC02A80	/* Bit Timing Configuration register 0                  */
    532. 

  532. #define CAN_TIMING			0xFFC02A84	/* Bit Timing Configuration register 1                  */
    533. 

  533. #define CAN_DEBUG			0xFFC02A88	/* Debug Register                                                               */
    534. 

  534. #define CAN_STATUS			0xFFC02A8C	/* Global Status Register                                               */
    535. 

  535. #define CAN_CEC				0xFFC02A90	/* Error Counter Register                                               */
    536. 

  536. #define CAN_GIS				0xFFC02A94	/* Global Interrupt Status Register                             */
    537. 

  537. #define CAN_GIM				0xFFC02A98	/* Global Interrupt Mask Register                               */
    538. 

  538. #define CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register                               */
    539. 

  539. #define CAN_CONTROL			0xFFC02AA0	/* Master Control Register                                              */
    540. 

  540. #define CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register                                   */
    541. 

  541. 

  542. #define CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature                    */
    543. 

  543. #define CAN_EWR				0xFFC02AB0	/* Programmable Warning Level                                   */
    544. 

  544. #define CAN_ESR				0xFFC02AB4	/* Error Status Register                                                */
    545. 

  545. #define CAN_UCREG			0xFFC02AC0	/* Universal Counter Register/Capture Register  */
    546. 

  546. #define CAN_UCCNT			0xFFC02AC4	/* Universal Counter                                                    */
    547. 

  547. #define CAN_UCRC			0xFFC02AC8	/* Universal Counter Force Reload Register              */
    548. 

  548. #define CAN_UCCNF			0xFFC02ACC	/* Universal Counter Configuration Register             */
    549. 

  549. 

  550. /* Mailbox Acceptance Masks 												*/
    551. 

  551. #define CAN_AM00L			0xFFC02B00	/* Mailbox 0 Low Acceptance Mask        */
    552. 

  552. #define CAN_AM00H			0xFFC02B04	/* Mailbox 0 High Acceptance Mask       */
    553. 

  553. #define CAN_AM01L			0xFFC02B08	/* Mailbox 1 Low Acceptance Mask        */
    554. 

  554. #define CAN_AM01H			0xFFC02B0C	/* Mailbox 1 High Acceptance Mask       */
    555. 

  555. #define CAN_AM02L			0xFFC02B10	/* Mailbox 2 Low Acceptance Mask        */
    556. 

  556. #define CAN_AM02H			0xFFC02B14	/* Mailbox 2 High Acceptance Mask       */
    557. 

  557. #define CAN_AM03L			0xFFC02B18	/* Mailbox 3 Low Acceptance Mask        */
    558. 

  558. #define CAN_AM03H			0xFFC02B1C	/* Mailbox 3 High Acceptance Mask       */
    559. 

  559. #define CAN_AM04L			0xFFC02B20	/* Mailbox 4 Low Acceptance Mask        */
    560. 

  560. #define CAN_AM04H			0xFFC02B24	/* Mailbox 4 High Acceptance Mask       */
    561. 

  561. #define CAN_AM05L			0xFFC02B28	/* Mailbox 5 Low Acceptance Mask        */
    562. 

  562. #define CAN_AM05H			0xFFC02B2C	/* Mailbox 5 High Acceptance Mask       */
    563. 

  563. #define CAN_AM06L			0xFFC02B30	/* Mailbox 6 Low Acceptance Mask        */
    564. 

  564. #define CAN_AM06H			0xFFC02B34	/* Mailbox 6 High Acceptance Mask       */
    565. 

  565. #define CAN_AM07L			0xFFC02B38	/* Mailbox 7 Low Acceptance Mask        */
    566. 

  566. #define CAN_AM07H			0xFFC02B3C	/* Mailbox 7 High Acceptance Mask       */
    567. 

  567. #define CAN_AM08L			0xFFC02B40	/* Mailbox 8 Low Acceptance Mask        */
    568. 

  568. #define CAN_AM08H			0xFFC02B44	/* Mailbox 8 High Acceptance Mask       */
    569. 

  569. #define CAN_AM09L			0xFFC02B48	/* Mailbox 9 Low Acceptance Mask        */
    570. 

  570. #define CAN_AM09H			0xFFC02B4C	/* Mailbox 9 High Acceptance Mask       */
    571. 

  571. #define CAN_AM10L			0xFFC02B50	/* Mailbox 10 Low Acceptance Mask       */
    572. 

  572. #define CAN_AM10H			0xFFC02B54	/* Mailbox 10 High Acceptance Mask      */
    573. 

  573. #define CAN_AM11L			0xFFC02B58	/* Mailbox 11 Low Acceptance Mask       */
    574. 

  574. #define CAN_AM11H			0xFFC02B5C	/* Mailbox 11 High Acceptance Mask      */
    575. 

  575. #define CAN_AM12L			0xFFC02B60	/* Mailbox 12 Low Acceptance Mask       */
    576. 

  576. #define CAN_AM12H			0xFFC02B64	/* Mailbox 12 High Acceptance Mask      */
    577. 

  577. #define CAN_AM13L			0xFFC02B68	/* Mailbox 13 Low Acceptance Mask       */
    578. 

  578. #define CAN_AM13H			0xFFC02B6C	/* Mailbox 13 High Acceptance Mask      */
    579. 

  579. #define CAN_AM14L			0xFFC02B70	/* Mailbox 14 Low Acceptance Mask       */
    580. 

  580. #define CAN_AM14H			0xFFC02B74	/* Mailbox 14 High Acceptance Mask      */
    581. 

  581. #define CAN_AM15L			0xFFC02B78	/* Mailbox 15 Low Acceptance Mask       */
    582. 

  582. #define CAN_AM15H			0xFFC02B7C	/* Mailbox 15 High Acceptance Mask      */
    583. 

  583. 

  584. #define CAN_AM16L			0xFFC02B80	/* Mailbox 16 Low Acceptance Mask       */
    585. 

  585. #define CAN_AM16H			0xFFC02B84	/* Mailbox 16 High Acceptance Mask      */
    586. 

  586. #define CAN_AM17L			0xFFC02B88	/* Mailbox 17 Low Acceptance Mask       */
    587. 

  587. #define CAN_AM17H			0xFFC02B8C	/* Mailbox 17 High Acceptance Mask      */
    588. 

  588. #define CAN_AM18L			0xFFC02B90	/* Mailbox 18 Low Acceptance Mask       */
    589. 

  589. #define CAN_AM18H			0xFFC02B94	/* Mailbox 18 High Acceptance Mask      */
    590. 

  590. #define CAN_AM19L			0xFFC02B98	/* Mailbox 19 Low Acceptance Mask       */
    591. 

  591. #define CAN_AM19H			0xFFC02B9C	/* Mailbox 19 High Acceptance Mask      */
    592. 

  592. #define CAN_AM20L			0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask       */
    593. 

  593. #define CAN_AM20H			0xFFC02BA4	/* Mailbox 20 High Acceptance Mask      */
    594. 

  594. #define CAN_AM21L			0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask       */
    595. 

  595. #define CAN_AM21H			0xFFC02BAC	/* Mailbox 21 High Acceptance Mask      */
    596. 

  596. #define CAN_AM22L			0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask       */
    597. 

  597. #define CAN_AM22H			0xFFC02BB4	/* Mailbox 22 High Acceptance Mask      */
    598. 

  598. #define CAN_AM23L			0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask       */
    599. 

  599. #define CAN_AM23H			0xFFC02BBC	/* Mailbox 23 High Acceptance Mask      */
    600. 

  600. #define CAN_AM24L			0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask       */
    601. 

  601. #define CAN_AM24H			0xFFC02BC4	/* Mailbox 24 High Acceptance Mask      */
    602. 

  602. #define CAN_AM25L			0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask       */
    603. 

  603. #define CAN_AM25H			0xFFC02BCC	/* Mailbox 25 High Acceptance Mask      */
    604. 

  604. #define CAN_AM26L			0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask       */
    605. 

  605. #define CAN_AM26H			0xFFC02BD4	/* Mailbox 26 High Acceptance Mask      */
    606. 

  606. #define CAN_AM27L			0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask       */
    607. 

  607. #define CAN_AM27H			0xFFC02BDC	/* Mailbox 27 High Acceptance Mask      */
    608. 

  608. #define CAN_AM28L			0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask       */
    609. 

  609. #define CAN_AM28H			0xFFC02BE4	/* Mailbox 28 High Acceptance Mask      */
    610. 

  610. #define CAN_AM29L			0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask       */
    611. 

  611. #define CAN_AM29H			0xFFC02BEC	/* Mailbox 29 High Acceptance Mask      */
    612. 

  612. #define CAN_AM30L			0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask       */
    613. 

  613. #define CAN_AM30H			0xFFC02BF4	/* Mailbox 30 High Acceptance Mask      */
    614. 

  614. #define CAN_AM31L			0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask       */
    615. 

  615. #define CAN_AM31H			0xFFC02BFC	/* Mailbox 31 High Acceptance Mask      */
    616. 

  616. 

  617. /* CAN Acceptance Mask Macros				*/
    618. 

  618. #define CAN_AM_L(x)		(CAN_AM00L+((x)*0x8))
    619. 

  619. #define CAN_AM_H(x)		(CAN_AM00H+((x)*0x8))
    620. 

  620. 

  621. /* Mailbox Registers																*/
    622. 

  622. #define CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0] Register        */
    623. 

  623. #define CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register       */
    624. 

  624. #define CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register       */
    625. 

  625. #define CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register       */
    626. 

  626. #define CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register          */
    627. 

  627. #define CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp Value Register          */
    628. 

  628. #define CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier Low Register            */
    629. 

  629. #define CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier High Register           */
    630. 

  630. 

  631. #define CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0] Register        */
    632. 

  632. #define CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register       */
    633. 

  633. #define CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register       */
    634. 

  634. #define CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register       */
    635. 

  635. #define CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register          */
    636. 

  636. #define CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp Value Register          */
    637. 

  637. #define CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier Low Register            */
    638. 

  638. #define CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier High Register           */
    639. 

  639. 

  640. #define CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0] Register        */
    641. 

  641. #define CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register       */
    642. 

  642. #define CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register       */
    643. 

  643. #define CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register       */
    644. 

  644. #define CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register          */
    645. 

  645. #define CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp Value Register          */
    646. 

  646. #define CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier Low Register            */
    647. 

  647. #define CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier High Register           */
    648. 

  648. 

  649. #define CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0] Register        */
    650. 

  650. #define CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register       */
    651. 

  651. #define CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register       */
    652. 

  652. #define CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register       */
    653. 

  653. #define CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register          */
    654. 

  654. #define CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp Value Register          */
    655. 

  655. #define CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier Low Register            */
    656. 

  656. #define CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier High Register           */
    657. 

  657. 

  658. #define CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0] Register        */
    659. 

  659. #define CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register       */
    660. 

  660. #define CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register       */
    661. 

  661. #define CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register       */
    662. 

  662. #define CAN_MB04_LENGTH		0xFFC02C90	/* Mailbox 4 Data Length Code Register          */
    663. 

  663. #define CAN_MB04_TIMESTAMP	0xFFC02C94	/* Mailbox 4 Time Stamp Value Register          */
    664. 

  664. #define CAN_MB04_ID0		0xFFC02C98	/* Mailbox 4 Identifier Low Register            */
    665. 

  665. #define CAN_MB04_ID1		0xFFC02C9C	/* Mailbox 4 Identifier High Register           */
    666. 

  666. 

  667. #define CAN_MB05_DATA0		0xFFC02CA0	/* Mailbox 5 Data Word 0 [15:0] Register        */
    668. 

  668. #define CAN_MB05_DATA1		0xFFC02CA4	/* Mailbox 5 Data Word 1 [31:16] Register       */
    669. 

  669. #define CAN_MB05_DATA2		0xFFC02CA8	/* Mailbox 5 Data Word 2 [47:32] Register       */
    670. 

  670. #define CAN_MB05_DATA3		0xFFC02CAC	/* Mailbox 5 Data Word 3 [63:48] Register       */
    671. 

  671. #define CAN_MB05_LENGTH		0xFFC02CB0	/* Mailbox 5 Data Length Code Register          */
    672. 

  672. #define CAN_MB05_TIMESTAMP	0xFFC02CB4	/* Mailbox 5 Time Stamp Value Register          */
    673. 

  673. #define CAN_MB05_ID0		0xFFC02CB8	/* Mailbox 5 Identifier Low Register            */
    674. 

  674. #define CAN_MB05_ID1		0xFFC02CBC	/* Mailbox 5 Identifier High Register           */
    675. 

  675. 

  676. #define CAN_MB06_DATA0		0xFFC02CC0	/* Mailbox 6 Data Word 0 [15:0] Register        */
    677. 

  677. #define CAN_MB06_DATA1		0xFFC02CC4	/* Mailbox 6 Data Word 1 [31:16] Register       */
    678. 

  678. #define CAN_MB06_DATA2		0xFFC02CC8	/* Mailbox 6 Data Word 2 [47:32] Register       */
    679. 

  679. #define CAN_MB06_DATA3		0xFFC02CCC	/* Mailbox 6 Data Word 3 [63:48] Register       */
    680. 

  680. #define CAN_MB06_LENGTH		0xFFC02CD0	/* Mailbox 6 Data Length Code Register          */
    681. 

  681. #define CAN_MB06_TIMESTAMP	0xFFC02CD4	/* Mailbox 6 Time Stamp Value Register          */
    682. 

  682. #define CAN_MB06_ID0		0xFFC02CD8	/* Mailbox 6 Identifier Low Register            */
    683. 

  683. #define CAN_MB06_ID1		0xFFC02CDC	/* Mailbox 6 Identifier High Register           */
    684. 

  684. 

  685. #define CAN_MB07_DATA0		0xFFC02CE0	/* Mailbox 7 Data Word 0 [15:0] Register        */
    686. 

  686. #define CAN_MB07_DATA1		0xFFC02CE4	/* Mailbox 7 Data Word 1 [31:16] Register       */
    687. 

  687. #define CAN_MB07_DATA2		0xFFC02CE8	/* Mailbox 7 Data Word 2 [47:32] Register       */
    688. 

  688. #define CAN_MB07_DATA3		0xFFC02CEC	/* Mailbox 7 Data Word 3 [63:48] Register       */
    689. 

  689. #define CAN_MB07_LENGTH		0xFFC02CF0	/* Mailbox 7 Data Length Code Register          */
    690. 

  690. #define CAN_MB07_TIMESTAMP	0xFFC02CF4	/* Mailbox 7 Time Stamp Value Register          */
    691. 

  691. #define CAN_MB07_ID0		0xFFC02CF8	/* Mailbox 7 Identifier Low Register            */
    692. 

  692. #define CAN_MB07_ID1		0xFFC02CFC	/* Mailbox 7 Identifier High Register           */
    693. 

  693. 

  694. #define CAN_MB08_DATA0		0xFFC02D00	/* Mailbox 8 Data Word 0 [15:0] Register        */
    695. 

  695. #define CAN_MB08_DATA1		0xFFC02D04	/* Mailbox 8 Data Word 1 [31:16] Register       */
    696. 

  696. #define CAN_MB08_DATA2		0xFFC02D08	/* Mailbox 8 Data Word 2 [47:32] Register       */
    697. 

  697. #define CAN_MB08_DATA3		0xFFC02D0C	/* Mailbox 8 Data Word 3 [63:48] Register       */
    698.