memoryCall.h 7.3 KB

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  1. /*
  2. * Copyright 2007-2009 Analog Devices Inc.
  3. *
  4. * Licensed under the GPL-2 or later.
  5. */
  6. #ifndef _BF548_IRQ_H_
  7. #define _BF548_IRQ_H_
  8. #include <mach-common/irq.h>
  9. #define NR_PERI_INTS (3 * 32)
  10. #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
  11. #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
  12. #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
  13. #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
  14. #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
  15. #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
  16. #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
  17. #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
  18. #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
  19. #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
  20. #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
  21. #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
  22. #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
  23. #define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
  24. #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
  25. #define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
  26. #define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
  27. #define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
  28. #define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
  29. #define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
  30. #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
  31. #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
  32. #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
  33. #define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
  34. #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
  35. #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
  36. #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
  37. #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
  38. #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
  39. #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
  40. #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
  41. #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
  42. #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
  43. #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
  44. #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
  45. #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
  46. #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
  47. #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
  48. #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
  49. #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
  50. #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
  51. #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
  52. #define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
  53. #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
  54. #define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
  55. #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
  56. #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
  57. #define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
  58. #define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
  59. #define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
  60. #define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
  61. #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
  62. #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
  63. #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
  64. #define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
  65. #define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
  66. #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
  67. #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
  68. #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
  69. #define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
  70. #define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
  71. #define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
  72. #define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
  73. #define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
  74. #define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
  75. #define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
  76. #define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
  77. #define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
  78. #define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
  79. #define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
  80. #define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
  81. #define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
  82. #define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
  83. #define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
  84. #define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
  85. #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
  86. #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
  87. #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
  88. #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
  89. #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
  90. #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
  91. #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
  92. #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
  93. #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
  94. #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
  95. #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
  96. #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
  97. #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
  98. #define SYS_IRQS IRQ_PINT3
  99. #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
  100. #define IRQ_PA0 BFIN_PA_IRQ(0)
  101. #define IRQ_PA1 BFIN_PA_IRQ(1)
  102. #define IRQ_PA2 BFIN_PA_IRQ(2)
  103. #define IRQ_PA3 BFIN_PA_IRQ(3)
  104. #define IRQ_PA4 BFIN_PA_IRQ(4)
  105. #define IRQ_PA5 BFIN_PA_IRQ(5)
  106. #define IRQ_PA6 BFIN_PA_IRQ(6)
  107. #define IRQ_PA7 BFIN_PA_IRQ(7)
  108. #define IRQ_PA8 BFIN_PA_IRQ(8)
  109. #define IRQ_PA9 BFIN_PA_IRQ(9)
  110. #define IRQ_PA10 BFIN_PA_IRQ(10)
  111. #define IRQ_PA11 BFIN_PA_IRQ(11)
  112. #define IRQ_PA12 BFIN_PA_IRQ(12)
  113. #define IRQ_PA13 BFIN_PA_IRQ(13)
  114. #define IRQ_PA14 BFIN_PA_IRQ(14)
  115. #define IRQ_PA15 BFIN_PA_IRQ(15)
  116. #define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
  117. #define IRQ_PB0 BFIN_PB_IRQ(0)
  118. #define IRQ_PB1 BFIN_PB_IRQ(1)
  119. #define IRQ_PB2 BFIN_PB_IRQ(2)
  120. #define IRQ_PB3 BFIN_PB_IRQ(3)
  121. #define IRQ_PB4 BFIN_PB_IRQ(4)
  122. #define IRQ_PB5 BFIN_PB_IRQ(5)
  123. #define IRQ_PB6 BFIN_PB_IRQ(6)
  124. #define IRQ_PB7 BFIN_PB_IRQ(7)
  125. #define IRQ_PB8 BFIN_PB_IRQ(8)
  126. #define IRQ_PB9 BFIN_PB_IRQ(9)
  127. #define IRQ_PB10 BFIN_PB_IRQ(10)
  128. #define IRQ_PB11 BFIN_PB_IRQ(11)
  129. #define IRQ_PB12 BFIN_PB_IRQ(12)
  130. #define IRQ_PB13 BFIN_PB_IRQ(13)
  131. #define IRQ_PB14 BFIN_PB_IRQ(14)
  132. #define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
  133. #define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
  134. #define IRQ_PC0 BFIN_PC_IRQ(0)
  135. #define IRQ_PC1 BFIN_PC_IRQ(1)
  136. #define IRQ_PC2 BFIN_PC_IRQ(2)
  137. #define IRQ_PC3 BFIN_PC_IRQ(3)
  138. #define IRQ_PC4 BFIN_PC_IRQ(4)
  139. #define IRQ_PC5 BFIN_PC_IRQ(5)
  140. #define IRQ_PC6 BFIN_PC_IRQ(6)
  141. #define IRQ_PC7 BFIN_PC_IRQ(7)
  142. #define IRQ_PC8 BFIN_PC_IRQ(8)
  143. #define IRQ_PC9 BFIN_PC_IRQ(9)
  144. #define IRQ_PC10 BFIN_PC_IRQ(10)
  145. #define IRQ_PC11 BFIN_PC_IRQ(11)