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memoryDefinitionAgingAnalysisData.h

memoryDefinitionAgingAnalysisData.h 11 KB
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  1. /*
    2. 

  2.  * OMAP3430 Power/Reset Management register bits
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2007-2008 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2007-2008 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Written by Paul Walmsley
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License version 2 as
    11. 

  11.  * published by the Free Software Foundation.
    12. 

  12.  */
    13. 

  13. #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
    14. 

  14. #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
    15. 

  15. 

  16. 

  17. #include "prm3xxx.h"
    18. 

  18. 

  19. /* Shared register bits */
    20. 

  20. 

  21. /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
    22. 

  22. #define OMAP3430_ON_SHIFT				24
    23. 

  23. #define OMAP3430_ON_MASK				(0xff << 24)
    24. 

  24. #define OMAP3430_ONLP_SHIFT				16
    25. 

  25. #define OMAP3430_ONLP_MASK				(0xff << 16)
    26. 

  26. #define OMAP3430_RET_SHIFT				8
    27. 

  27. #define OMAP3430_RET_MASK				(0xff << 8)
    28. 

  28. #define OMAP3430_OFF_SHIFT				0
    29. 

  29. #define OMAP3430_OFF_MASK				(0xff << 0)
    30. 

  30. 

  31. /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
    32. 

  32. #define OMAP3430_ERROROFFSET_SHIFT			24
    33. 

  33. #define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
    34. 

  34. #define OMAP3430_ERRORGAIN_SHIFT			16
    35. 

  35. #define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
    36. 

  36. #define OMAP3430_INITVOLTAGE_SHIFT			8
    37. 

  37. #define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
    38. 

  38. #define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
    39. 

  39. #define OMAP3430_INITVDD_MASK				(1 << 2)
    40. 

  40. #define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
    41. 

  41. #define OMAP3430_VPENABLE_MASK				(1 << 0)
    42. 

  42. 

  43. /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
    44. 

  44. #define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
    45. 

  45. #define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
    46. 

  46. #define OMAP3430_VSTEPMIN_SHIFT				0
    47. 

  47. #define OMAP3430_VSTEPMIN_MASK				(0xff << 0)
    48. 

  48. 

  49. /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
    50. 

  50. #define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
    51. 

  51. #define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
    52. 

  52. #define OMAP3430_VSTEPMAX_SHIFT				0
    53. 

  53. #define OMAP3430_VSTEPMAX_MASK				(0xff << 0)
    54. 

  54. 

  55. /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
    56. 

  56. #define OMAP3430_VDDMAX_SHIFT				24
    57. 

  57. #define OMAP3430_VDDMAX_MASK				(0xff << 24)
    58. 

  58. #define OMAP3430_VDDMIN_SHIFT				16
    59. 

  59. #define OMAP3430_VDDMIN_MASK				(0xff << 16)
    60. 

  60. #define OMAP3430_TIMEOUT_SHIFT				0
    61. 

  61. #define OMAP3430_TIMEOUT_MASK				(0xffff << 0)
    62. 

  62. 

  63. /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
    64. 

  64. #define OMAP3430_VPVOLTAGE_SHIFT			0
    65. 

  65. #define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
    66. 

  66. 

  67. /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
    68. 

  68. #define OMAP3430_VPINIDLE_MASK				(1 << 0)
    69. 

  69. 

  70. /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
    71. 

  71. #define OMAP3430_EN_PER_SHIFT				7
    72. 

  72. #define OMAP3430_EN_PER_MASK				(1 << 7)
    73. 

  73. 

  74. /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
    75. 

  75. #define OMAP3430_MEMORYCHANGE_MASK			(1 << 3)
    76. 

  76. 

  77. /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
    78. 

  78. #define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
    79. 

  79. 

  80. /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
    81. 

  81. #define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
    82. 

  82. 

  83. /*
    84. 

  84.  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
    85. 

  85.  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
    86. 

  86.  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
    87. 

  87.  */
    88. 

  88. #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT		0
    89. 

  89. #define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
    90. 

  90. 

  91. /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
    92. 

  92. #define OMAP3430_WKUP_ST_MASK				(1 << 0)
    93. 

  93. 

  94. /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
    95. 

  95. #define OMAP3430_WKUP_EN_MASK				(1 << 0)
    96. 

  96. 

  97. /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
    98. 

  98. #define OMAP3430_GRPSEL_MMC2_MASK			(1 << 25)
    99. 

  99. #define OMAP3430_GRPSEL_MMC1_MASK			(1 << 24)
    100. 

  100. #define OMAP3430_GRPSEL_MCSPI4_MASK			(1 << 21)
    101. 

  101. #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20)
    102. 

  102. #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19)
    103. 

  103. #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18)
    104. 

  104. #define OMAP3430_GRPSEL_I2C3_SHIFT			17
    105. 

  105. #define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17)
    106. 

  106. #define OMAP3430_GRPSEL_I2C2_SHIFT			16
    107. 

  107. #define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16)
    108. 

  108. #define OMAP3430_GRPSEL_I2C1_SHIFT			15
    109. 

  109. #define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15)
    110. 

  110. #define OMAP3430_GRPSEL_UART2_MASK			(1 << 14)
    111. 

  111. #define OMAP3430_GRPSEL_UART1_MASK			(1 << 13)
    112. 

  112. #define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12)
    113. 

  113. #define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11)
    114. 

  114. #define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
    115. 

  115. #define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
    116. 

  116. #define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4)
    117. 

  117. #define OMAP3430_GRPSEL_D2D_MASK			(1 << 3)
    118. 

  118. 

  119. /*
    120. 

  120.  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
    121. 

  121.  * PM_PWSTCTRL_PER shared bits
    122. 

  122.  */
    123. 

  123. #define OMAP3430_MEMONSTATE_SHIFT			16
    124. 

  124. #define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
    125. 

  125. #define OMAP3430_MEMRETSTATE_MASK			(1 << 8)
    126. 

  126. 

  127. /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
    128. 

  128. #define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
    129. 

  129. #define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
    130. 

  130. #define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
    131. 

  131. #define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
    132. 

  132. #define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
    133. 

  133. #define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
    134. 

  134. #define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
    135. 

  135. #define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10)
    136. 

  136. #define OMAP3430_GRPSEL_GPT8_MASK			(1 << 9)
    137. 

  137. #define OMAP3430_GRPSEL_GPT7_MASK			(1 << 8)
    138. 

  138. #define OMAP3430_GRPSEL_GPT6_MASK			(1 << 7)
    139. 

  139. #define OMAP3430_GRPSEL_GPT5_MASK			(1 << 6)
    140. 

  140. #define OMAP3430_GRPSEL_GPT4_MASK			(1 << 5)
    141. 

  141. #define OMAP3430_GRPSEL_GPT3_MASK			(1 << 4)
    142. 

  142. #define OMAP3430_GRPSEL_GPT2_MASK			(1 << 3)
    143. 

  143. #define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
    144. 

  144. #define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
    145. 

  145. #define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)
    146. 

  146. 

  147. /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
    148. 

  148. #define OMAP3430_GRPSEL_IO_MASK				(1 << 8)
    149. 

  149. #define OMAP3430_GRPSEL_SR2_MASK			(1 << 7)
    150. 

  150. #define OMAP3430_GRPSEL_SR1_MASK			(1 << 6)
    151. 

  151. #define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
    152. 

  152. #define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
    153. 

  153. #define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)
    154. 

  154. 

  155. /* Bits specific to each register */
    156. 

  156. 

  157. /* RM_RSTCTRL_IVA2 */
    158. 

  158. #define OMAP3430_RST3_IVA2_MASK				(1 << 2)
    159. 

  159. #define OMAP3430_RST2_IVA2_MASK				(1 << 1)
    160. 

  160. #define OMAP3430_RST1_IVA2_MASK				(1 << 0)
    161. 

  161. 

  162. /* RM_RSTST_IVA2 specific bits */
    163. 

  163. #define OMAP3430_EMULATION_VSEQ_RST_MASK		(1 << 13)
    164. 

  164. #define OMAP3430_EMULATION_VHWA_RST_MASK		(1 << 12)
    165. 

  165. #define OMAP3430_EMULATION_IVA2_RST_MASK		(1 << 11)
    166. 

  166. #define OMAP3430_IVA2_SW_RST3_MASK			(1 << 10)
    167. 

  167. #define OMAP3430_IVA2_SW_RST2_MASK			(1 << 9)
    168. 

  168. #define OMAP3430_IVA2_SW_RST1_MASK			(1 << 8)
    169. 

  169. 

  170. /* PM_WKDEP_IVA2 specific bits */
    171. 

  171. 

  172. /* PM_PWSTCTRL_IVA2 specific bits */
    173. 

  173. #define OMAP3430_L2FLATMEMONSTATE_SHIFT			22
    174. 

  174. #define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
    175. 

  175. #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT		20
    176. 

  176. #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
    177. 

  177. #define OMAP3430_L1FLATMEMONSTATE_SHIFT			18
    178. 

  178. #define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
    179. 

  179. #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT		16
    180. 

  180. #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
    181. 

  181. #define OMAP3430_L2FLATMEMRETSTATE_MASK			(1 << 11)
    182. 

  182. #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK		(1 << 10)
    183. 

  183. #define OMAP3430_L1FLATMEMRETSTATE_MASK			(1 << 9)
    184. 

  184. #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK		(1 << 8)
    185. 

  185. 

  186. /* PM_PWSTST_IVA2 specific bits */
    187. 

  187. #define OMAP3430_L2FLATMEMSTATEST_SHIFT			10
    188. 

  188. #define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
    189. 

  189. #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT		8
    190. 

  190. #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
    191. 

  191. #define OMAP3430_L1FLATMEMSTATEST_SHIFT			6
    192. 

  192. #define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
    193. 

  193. #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT		4
    194. 

  194. #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)
    195. 

  195. 

  196. /* PM_PREPWSTST_IVA2 specific bits */
    197. 

  197. #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT		10
    198. 

  198. #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
    199. 

  199. #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT	8
    200. 

  200. #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
    201. 

  201. #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT		6
    202. 

  202. #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK			(0x3 << 6)
    203. 

  203. #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT	4
    204. 

  204. #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK		(0x3 << 4)
    205. 

  205. 

  206. /* PRM_IRQSTATUS_IVA2 specific bits */
    207. 

  207. #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK	(1 << 2)
    208. 

  208. #define OMAP3430_FORCEWKUP_ST_MASK			(1 << 1)
    209. 

  209. 

  210. /* PRM_IRQENABLE_IVA2 specific bits */
    211. 

  211. #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK	(1 << 2)
    212. 

  212. #define OMAP3430_FORCEWKUP_EN_MASK				(1 << 1)
    213. 

  213. 

  214. /* PRM_REVISION specific bits */
    215. 

  215. 

  216. /* PRM_SYSCONFIG specific bits */
    217. 

  217. 

  218. /* PRM_IRQSTATUS_MPU specific bits */
    219. 

  219. #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
    220. 

  220. #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK		(1 << 25)
    221. 

  221. #define OMAP3430_VC_TIMEOUTERR_ST_MASK			(1 << 24)
    222. 

  222. #define OMAP3430_VC_RAERR_ST_MASK			(1 << 23)
    223. 

  223. #define OMAP3430_VC_SAERR_ST_MASK			(1 << 22)
    224. 

  224. #define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
    225. 

  225. #define OMAP3430_VP2_EQVALUE_ST_MASK			(1 << 20)
    226. 

  226. #define OMAP3430_VP2_NOSMPSACK_ST_MASK			(1 << 19)
    227. 

  227. #define OMAP3430_VP2_MAXVDD_ST_MASK			(1 << 18)
    228. 

  228. #define OMAP3430_VP2_MINVDD_ST_MASK			(1 << 17)
    229. 

  229. #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK		(1 << 16)
    230. 

  230. #define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
    231. 

  231. #define OMAP3430_VP1_EQVALUE_ST_MASK			(1 << 14)
    232. 

  232. #define OMAP3430_VP1_NOSMPSACK_ST_MASK			(1 << 13)
    233. 

  233. #define OMAP3430_VP1_MAXVDD_ST_MASK			(1 << 12)
    234. 

  234. #define OMAP3430_VP1_MINVDD_ST_MASK			(1 << 11)
    235. 

  235. #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK		(1 << 10)
    236. 

  236. #define OMAP3430_IO_ST_MASK				(1 << 9)
    237. 

  237. #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK	(1 << 8)
    238. 

  238. #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
    239. 

  239. #define OMAP3430_MPU_DPLL_ST_MASK			(1 << 7)
    240. 

  240. #define OMAP3430_MPU_DPLL_ST_SHIFT			7
    241. 

  241. #define OMAP3430_PERIPH_DPLL_ST_MASK			(1 << 6)
    242. 

  242. #define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
    243. 

  243. #define OMAP3430_CORE_DPLL_ST_MASK			(1 << 5)
    244. 

  244. #define OMAP3430_CORE_DPLL_ST_SHIFT			5
    245. 

  245. #define OMAP3430_TRANSITION_ST_MASK			(1 << 4)
    246. 

  246. #define OMAP3430_EVGENOFF_ST_MASK			(1 << 3)
    247. 

  247. #define OMAP3430_EVGENON_ST_MASK			(1 << 2)
    248. 

  248. #define OMAP3430_FS_USB_WKUP_ST_MASK			(1 << 1)
    249. 

  249. 

  250. /* PRM_IRQENABLE_MPU specific bits */
    251. 

  251. #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
    252. 

  252. #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK		(1 << 25)
    253. 

  253. #define OMAP3430_VC_TIMEOUTERR_EN_MASK				(1 << 24)
    254. 

  254. #define OMAP3430_VC_RAERR_EN_MASK				(1 << 23)
    255. 

  255. #define OMAP3430_VC_SAERR_EN_MASK				(1 << 22)
    256. 

  256. #define OMAP3430_VP2_TRANXDONE_EN_MASK				(1 << 21)
    257. 

  257. #define OMAP3430_VP2_EQVALUE_EN_MASK				(1 << 20)
    258. 

  258. #define OMAP3430_VP2_NOSMPSACK_EN_MASK				(1 << 19)
    259. 

  259. #define OMAP3430_VP2_MAXVDD_EN_MASK				(1 << 18)
    260. 

  260. #define OMAP3430_VP2_MINVDD_EN_MASK				(1 << 17)
    261. 

  261. #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK			(1 << 16)
    262. 

  262. #define OMAP3430_VP1_TRANXDONE_EN_MASK				(1 << 15)
    263. 

  263. #define OMAP3430_VP1_EQVALUE_EN_MASK				(1 << 14)
    264. 

  264. #define OMAP3430_VP1_NOSMPSACK_EN_MASK				(1 << 13)
    265. 

  265. #define OMAP3430_VP1_MAXVDD_EN_MASK				(1 << 12)
    266. 

  266. #define OMAP3430_VP1_MINVDD_EN_MASK				(1 << 11)
    267. 

  267. #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK			(1 << 10)
    268. 

  268. #define OMAP3430_IO_EN_MASK					(1 << 9)
    269. 

  269. #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK	(1 << 8)
    270. 

  270. #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
    271. 

  271. #define OMAP3430_MPU_DPLL_RECAL_EN_MASK				(1 << 7)
    272. 

  272. #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
    273. 

  273. #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK			(1 << 6)
    274. 

  274. #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
    275. 

  275. #define OMAP3430_CORE_DPLL_RECAL_EN_MASK			(1 << 5)
    276. 

  276. #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
    277. 

  277. #define OMAP3430_TRANSITION_EN_MASK				(1 << 4)
    278. 

  278. #define OMAP3430_EVGENOFF_EN_MASK				(1 << 3)
    279. 

  279. #define OMAP3430_EVGENON_EN_MASK				(1 << 2)
    280. 

  280. #define OMAP3430_FS_USB_WKUP_EN_MASK				(1 << 1)
    281. 

  281. 

  282. /* RM_RSTST_MPU specific bits */
    283. 

  283. #define OMAP3430_EMULATION_MPU_RST_MASK			(1 << 11)
    284. 

  284. 

  285. /* PM_WKDEP_MPU specific bits */
    286. 

  286. #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
    287. 

  287. #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK		(1 << 5)
    288. 

  288. #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
    289. 

  289. #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK		(1 << 2)
    290. 

  290. 

  291. /* PM_EVGENCTRL_MPU */
    292. 

  292. #define OMAP3430_OFFLOADMODE_SHIFT			3
    293.