varianceMemoryDefinition.h 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139
  1. /***********************************
  2. * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
  3. ***********************************
  4. *
  5. ***************************************
  6. * Definitions of the QUICC registers
  7. ***************************************
  8. */
  9. #ifndef __REGISTERS_H
  10. #define __REGISTERS_H
  11. #define CLEAR_BIT(x, bit) x =bit
  12. /*****************************************************************
  13. Command Register
  14. *****************************************************************/
  15. /* bit fields within command register */
  16. #define SOFTWARE_RESET 0x8000
  17. #define CMD_OPCODE 0x0f00
  18. #define CMD_CHANNEL 0x00f0
  19. #define CMD_FLAG 0x0001
  20. /* general command opcodes */
  21. #define INIT_RXTX_PARAMS 0x0000
  22. #define INIT_RX_PARAMS 0x0100
  23. #define INIT_TX_PARAMS 0x0200
  24. #define ENTER_HUNT_MODE 0x0300
  25. #define STOP_TX 0x0400
  26. #define GR_STOP_TX 0x0500
  27. #define RESTART_TX 0x0600
  28. #define CLOSE_RX_BD 0x0700
  29. #define SET_ENET_GROUP 0x0800
  30. #define RESET_ENET_GROUP 0x0900
  31. /* quicc32 CP commands */
  32. #define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */
  33. #define ENTER_HUNT_MODE_32 0x1e00
  34. /* quicc32 mask/event SCC register */
  35. #define GOV 0x01
  36. #define GUN 0x02
  37. #define GINT 0x04
  38. #define IQOV 0x08
  39. /* Timer commands */
  40. #define SET_TIMER 0x0800
  41. /* Multi channel Interrupt structure */
  42. #define INTR_VALID 0x8000 /* Valid interrupt entry */
  43. #define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */
  44. #define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */
  45. #define INTR_MASK_BITS 0x383f
  46. /*
  47. * General SCC mode register (GSMR)
  48. */
  49. #define MODE_HDLC 0x0
  50. #define MODE_APPLE_TALK 0x2
  51. #define MODE_SS7 0x3
  52. #define MODE_UART 0x4
  53. #define MODE_PROFIBUS 0x5
  54. #define MODE_ASYNC_HDLC 0x6
  55. #define MODE_V14 0x7
  56. #define MODE_BISYNC 0x8
  57. #define MODE_DDCMP 0x9
  58. #define MODE_MULTI_CHANNEL 0xa
  59. #define MODE_ETHERNET 0xc
  60. #define DIAG_NORMAL 0x0
  61. #define DIAG_LOCAL_LPB 0x1
  62. #define DIAG_AUTO_ECHO 0x2
  63. #define DIAG_LBP_ECHO 0x3
  64. /* For RENC and TENC fields in GSMR */
  65. #define ENC_NRZ 0x0
  66. #define ENC_NRZI 0x1
  67. #define ENC_FM0 0x2
  68. #define ENC_MANCH 0x4
  69. #define ENC_DIFF_MANC 0x6
  70. /* For TDCR and RDCR fields in GSMR */
  71. #define CLOCK_RATE_1 0x0
  72. #define CLOCK_RATE_8 0x1
  73. #define CLOCK_RATE_16 0x2
  74. #define CLOCK_RATE_32 0x3
  75. #define TPP_00 0x0
  76. #define TPP_10 0x1
  77. #define TPP_01 0x2
  78. #define TPP_11 0x3
  79. #define TPL_NO 0x0
  80. #define TPL_8 0x1
  81. #define TPL_16 0x2
  82. #define TPL_32 0x3
  83. #define TPL_48 0x4
  84. #define TPL_64 0x5
  85. #define TPL_128 0x6
  86. #define TSNC_INFINITE 0x0
  87. #define TSNC_14_65 0x1
  88. #define TSNC_4_15 0x2
  89. #define TSNC_3_1 0x3
  90. #define EDGE_BOTH 0x0
  91. #define EDGE_POS 0x1
  92. #define EDGE_NEG 0x2
  93. #define EDGE_NO 0x3
  94. #define SYNL_NO 0x0
  95. #define SYNL_4 0x1
  96. #define SYNL_8 0x2
  97. #define SYNL_16 0x3
  98. #define TCRC_CCITT16 0x0
  99. #define TCRC_CRC16 0x1
  100. #define TCRC_CCITT32 0x2
  101. /*****************************************************************
  102. TODR (Transmit on demand) Register
  103. *****************************************************************/
  104. #define TODR_TOD 0x8000 /* Transmit on demand */
  105. /*****************************************************************
  106. CICR register settings
  107. *****************************************************************/
  108. /* note that relative irq priorities of the SCCs can be reordered
  109. * if desired - see p. 7-377 of the MC68360UM */
  110. #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
  111. #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
  112. #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
  113. #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */