Etusivu Tutki Apua
Kirjaudu sisään
lixinru
/
aiot
1
0
Fork 0
Tiedostot Ongelmat 0 Pull-pyynnöt 0 Wiki
Puu: c190c9469b
Branchit Tagit
aiot
/
waterDataStatisticsCrossAssociation
/
dataAssociation
/
rtuHydrantCorrelationCalculation.h

rtuHydrantCorrelationCalculation.h 8.1 KB
Historia Raaka

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114 
  1. /*
    2. 

  2.  * Copyright 2007-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF525_H
    8. 

  8. #define _DEF_BF525_H
    9. 

  9. 

  10. /* BF525 is BF522 + USB */
    11. 

  11. #include "defBF522.h"
    12. 

  12. 

  13. /* USB Control Registers */
    14. 

  14. 

  15. #define                        USB_FADDR  0xffc03800   /* Function address register */
    16. 

  16. #define                        USB_POWER  0xffc03804   /* Power management register */
    17. 

  17. #define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
    18. 

  18. #define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
    19. 

  19. #define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
    20. 

  20. #define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
    21. 

  21. #define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
    22. 

  22. #define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
    23. 

  23. #define                        USB_FRAME  0xffc03820   /* USB frame number */
    24. 

  24. #define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
    25. 

  25. #define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
    26. 

  26. #define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
    27. 

  27. #define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
    28. 

  28. 

  29. /* USB Packet Control Registers */
    30. 

  30. 

  31. #define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
    32. 

  32. #define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    33. 

  33. #define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    34. 

  34. #define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
    35. 

  35. #define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
    36. 

  36. #define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    37. 

  37. #define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    38. 

  38. #define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
    39. 

  39. #define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    40. 

  40. #define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    41. 

  41. #define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
    42. 

  42. #define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
    43. 

  43. #define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
    44. 

  44. 

  45. /* USB Endpoint FIFO Registers */
    46. 

  46. 

  47. #define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
    48. 

  48. #define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
    49. 

  49. #define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
    50. 

  50. #define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
    51. 

  51. #define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
    52. 

  52. #define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
    53. 

  53. #define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
    54. 

  54. #define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
    55. 

  55. 

  56. /* USB OTG Control Registers */
    57. 

  57. 

  58. #define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
    59. 

  59. #define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
    60. 

  60. #define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
    61. 

  61. 

  62. /* USB Phy Control Registers */
    63. 

  63. 

  64. #define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
    65. 

  65. #define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
    66. 

  66. #define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
    67. 

  67. #define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
    68. 

  68. #define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
    69. 

  69. 

  70. /* (APHY_CNTRL is for ADI usage only) */
    71. 

  71. 

  72. #define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
    73. 

  73. 

  74. /* (APHY_CALIB is for ADI usage only) */
    75. 

  75. 

  76. #define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
    77. 

  77. 

  78. #define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
    79. 

  79. 

  80. /* (PHY_TEST is for ADI usage only) */
    81. 

  81. 

  82. #define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
    83. 

  83. 

  84. #define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
    85. 

  85. #define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
    86. 

  86. 

  87. /* USB Endpoint 0 Control Registers */
    88. 

  88. 

  89. #define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
    90. 

  90. #define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
    91. 

  91. #define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
    92. 

  92. #define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
    93. 

  93. #define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
    94. 

  94. #define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
    95. 

  95. #define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
    96. 

  96. #define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
    97. 

  97. #define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
    98. 

  98. #define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
    99. 

  99. 

  100. /* USB Endpoint 1 Control Registers */
    101. 

  101. 

  102. #define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
    103. 

  103. #define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
    104. 

  104. #define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
    105. 

  105. #define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
    106. 

  106. #define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
    107. 

  107. #define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
    108. 

  108. #define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
    109. 

  109. #define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
    110. 

  110. #define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
    111. 

  111. #define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
    112. 

  112. 

  113. /* USB Endpoint 2 Control Registers */
    114. 

  114.