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- /*
- * OMAP44xx CM1 instance offset macros
- *
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
- * or "OMAP4430".
- */
- #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
- #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
- /* CM1 base address */
- #define OMAP4430_CM1_BASE 0x4a004000
- #define OMAP44XX_CM1_REGADDR(inst, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
- /* CM1 instances */
- #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
- #define OMAP4430_CM1_CKGEN_INST 0x0100
- #define OMAP4430_CM1_MPU_INST 0x0300
- #define OMAP4430_CM1_TESLA_INST 0x0400
- #define OMAP4430_CM1_ABE_INST 0x0500
- #define OMAP4430_CM1_RESTORE_INST 0x0e00
- #define OMAP4430_CM1_INSTR_INST 0x0f00
- /* CM1 clockdomain register offsets (from instance start) */
- #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
- #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
- #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
- /* CM1 */
- /* CM1.OCP_SOCKET_CM1 register offsets */
- #define OMAP4_REVISION_CM1_OFFSET 0x0000
- #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
- #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
- #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
- /* CM1.CKGEN_CM1 register offsets */
- #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
- #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
- #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
- #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
- #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
- #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
- #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
- #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
- #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
- #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
- #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
- #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
- #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
- #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
- #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
- #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
- #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
- #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
- #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
- #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
- #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
- #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
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