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memoryCall.h

memoryCall.h 40 KB
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  1. /*
    2. 

  2.  * Copyright 2011 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later.
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF60X_H
    8. 

  8. #define _CDEF_BF60X_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
    15. 

  15. 

  16. #define bfin_read_CHIPID()		bfin_read32(CHIPID)
    17. 

  17. #define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
    18. 

  18. 

  19. /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
    20. 

  20. 

  21. /* SEC0 Registers */
    22. 

  22. #define bfin_read_SEC0_CCTL()		bfin_read32(SEC0_CCTL)
    23. 

  23. #define bfin_write_SEC0_CCTL(val)	bfin_write32(SEC0_CCTL, val)
    24. 

  24. #define bfin_read_SEC0_CSID()		bfin_read32(SEC0_CSID)
    25. 

  25. #define bfin_write_SEC0_CSID(val)	bfin_write32(SEC0_CSID, val)
    26. 

  26. #define bfin_read_SEC_GCTL()		bfin_read32(SEC_GCTL)
    27. 

  27. #define bfin_write_SEC_GCTL(val)	bfin_write32(SEC_GCTL, val)
    28. 

  28. 

  29. #define bfin_read_SEC_FCTL()		bfin_read32(SEC_FCTL)
    30. 

  30. #define bfin_write_SEC_FCTL(val)	bfin_write32(SEC_FCTL, val)
    31. 

  31. 

  32. #define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC_SCTL0 + (sid) * 8))
    33. 

  33. #define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC_SCTL0 + (sid) * 8), val)
    34. 

  34. 

  35. #define bfin_read_SEC_SSTAT(sid)	bfin_read32((SEC_SSTAT0 + (sid) * 8))
    36. 

  36. #define bfin_write_SEC_SSTAT(sid, val)	bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
    37. 

  37. 

  38. /* RCU0 Registers */
    39. 

  39. #define bfin_read_RCU0_CTL()		bfin_read32(RCU0_CTL)
    40. 

  40. #define bfin_write_RCU0_CTL(val)	bfin_write32(RCU0_CTL, val)
    41. 

  41. 

  42. /* Watchdog Timer Registers */
    43. 

  43. #define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
    44. 

  44. #define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
    45. 

  45. #define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
    46. 

  46. #define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
    47. 

  47. #define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
    48. 

  48. #define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)
    49. 

  49. 

  50. /* RTC Registers */
    51. 

  51. 

  52. /* UART0 Registers */
    53. 

  53. 

  54. #define bfin_read_UART0_REVID()		bfin_read32(UART0_REVID)
    55. 

  55. #define bfin_write_UART0_REVID(val)	bfin_write32(UART0_REVID, val)
    56. 

  56. #define bfin_read_UART0_GCTL()		bfin_read32(UART0_GCTL)
    57. 

  57. #define bfin_write_UART0_GCTL(val)	bfin_write32(UART0_GCTL, val)
    58. 

  58. #define bfin_read_UART0_STAT()		bfin_read32(UART0_STAT)
    59. 

  59. #define bfin_write_UART0_STAT(val)	bfin_write32(UART0_STAT, val)
    60. 

  60. #define bfin_read_UART0_SCR()		bfin_read32(UART0_SCR)
    61. 

  61. #define bfin_write_UART0_SCR(val)	bfin_write32(UART0_SCR, val)
    62. 

  62. #define bfin_read_UART0_CLK()		bfin_read32(UART0_CLK)
    63. 

  63. #define bfin_write_UART0_CLK(val)	bfin_write32(UART0_CLK, val)
    64. 

  64. #define bfin_read_UART0_IER()		bfin_read32(UART0_IER)
    65. 

  65. #define bfin_write_UART0_IER(val)	bfin_write32(UART0_IER, val)
    66. 

  66. #define bfin_read_UART0_IER_SET()	bfin_read32(UART0_IER_SET)
    67. 

  67. #define bfin_write_UART0_IER_SET(val)	bfin_write32(UART0_IER_SET, val)
    68. 

  68. #define bfin_read_UART0_IER_CLEAR()	bfin_read32(UART0_IER_CLEAR)
    69. 

  69. #define bfin_write_UART0_IER_CLEAR(val)	bfin_write32(UART0_IER_CLEAR, val)
    70. 

  70. #define bfin_read_UART0_RBR()		bfin_read32(UART0_RBR)
    71. 

  71. #define bfin_write_UART0_RBR(val)	bfin_write32(UART0_RBR, val)
    72. 

  72. #define bfin_read_UART0_THR()		bfin_read32(UART0_THR)
    73. 

  73. #define bfin_write_UART0_THR(val)	bfin_write32(UART0_THR, val)
    74. 

  74. #define bfin_read_UART0_TAIP()		bfin_read32(UART0_TAIP)
    75. 

  75. #define bfin_write_UART0_TAIP(val)	bfin_write32(UART0_TAIP, val)
    76. 

  76. #define bfin_read_UART0_TSR()		bfin_read32(UART0_TSR)
    77. 

  77. #define bfin_write_UART0_TSR(val)	bfin_write32(UART0_TSR, val)
    78. 

  78. #define bfin_read_UART0_RSR()		bfin_read32(UART0_RSR)
    79. 

  79. #define bfin_write_UART0_RSR(val)	bfin_write32(UART0_RSR, val)
    80. 

  80. #define bfin_read_UART0_TXCNT()		bfin_read32(UART0_TXCNT)
    81. 

  81. #define bfin_write_UART0_TXCNT(val)	bfin_write32(UART0_TXCNT, val)
    82. 

  82. #define bfin_read_UART0_RXCNT()		bfin_read32(UART0_RXCNT)
    83. 

  83. #define bfin_write_UART0_RXCNT(val)	bfin_write32(UART0_RXCNT, val)
    84. 

  84. 

  85. /* UART1 Registers */
    86. 

  86. 

  87. #define bfin_read_UART1_REVID()		bfin_read32(UART1_REVID)
    88. 

  88. #define bfin_write_UART1_REVID(val)	bfin_write32(UART1_REVID, val)
    89. 

  89. #define bfin_read_UART1_GCTL()		bfin_read32(UART1_GCTL)
    90. 

  90. #define bfin_write_UART1_GCTL(val)	bfin_write32(UART1_GCTL, val)
    91. 

  91. #define bfin_read_UART1_STAT()		bfin_read32(UART1_STAT)
    92. 

  92. #define bfin_write_UART1_STAT(val)	bfin_write32(UART1_STAT, val)
    93. 

  93. #define bfin_read_UART1_SCR()		bfin_read32(UART1_SCR)
    94. 

  94. #define bfin_write_UART1_SCR(val)	bfin_write32(UART1_SCR, val)
    95. 

  95. #define bfin_read_UART1_CLK()		bfin_read32(UART1_CLK)
    96. 

  96. #define bfin_write_UART1_CLK(val)	bfin_write32(UART1_CLK, val)
    97. 

  97. #define bfin_read_UART1_IER()		bfin_read32(UART1_IER)
    98. 

  98. #define bfin_write_UART1_IER(val)	bfin_write32(UART1_IER, val)
    99. 

  99. #define bfin_read_UART1_IER_SET()	bfin_read32(UART1_IER_SET)
    100. 

  100. #define bfin_write_UART1_IER_SET(val)	bfin_write32(UART1_IER_SET, val)
    101. 

  101. #define bfin_read_UART1_IER_CLEAR()	bfin_read32(UART1_IER_CLEAR)
    102. 

  102. #define bfin_write_UART1_IER_CLEAR(val)	bfin_write32(UART1_IER_CLEAR, val)
    103. 

  103. #define bfin_read_UART1_RBR()		bfin_read32(UART1_RBR)
    104. 

  104. #define bfin_write_UART1_RBR(val)	bfin_write32(UART1_RBR, val)
    105. 

  105. #define bfin_read_UART1_THR()		bfin_read32(UART1_THR)
    106. 

  106. #define bfin_write_UART1_THR(val)	bfin_write32(UART1_THR, val)
    107. 

  107. #define bfin_read_UART1_TAIP()		bfin_read32(UART1_TAIP)
    108. 

  108. #define bfin_write_UART1_TAIP(val)	bfin_write32(UART1_TAIP, val)
    109. 

  109. #define bfin_read_UART1_TSR()		bfin_read32(UART1_TSR)
    110. 

  110. #define bfin_write_UART1_TSR(val)	bfin_write32(UART1_TSR, val)
    111. 

  111. #define bfin_read_UART1_RSR()		bfin_read32(UART1_RSR)
    112. 

  112. #define bfin_write_UART1_RSR(val)	bfin_write32(UART1_RSR, val)
    113. 

  113. #define bfin_read_UART1_TXCNT()		bfin_read32(UART1_TXCNT)
    114. 

  114. #define bfin_write_UART1_TXCNT(val)	bfin_write32(UART1_TXCNT, val)
    115. 

  115. #define bfin_read_UART1_RXCNT()		bfin_read32(UART1_RXCNT)
    116. 

  116. #define bfin_write_UART1_RXCNT(val)	bfin_write32(UART1_RXCNT, val)
    117. 

  117. 

  118. 

  119. /* SPI0 Registers */
    120. 

  120. 

  121. #define bfin_read_SPI0_CTL()		bfin_read32(SPI0_CTL)
    122. 

  122. #define bfin_write_SPI0_CTL(val)	bfin_write32(SPI0_CTL, val)
    123. 

  123. #define bfin_read_SPI0_RXCTL()		bfin_read32(SPI0_RXCTL)
    124. 

  124. #define bfin_write_SPI0_RXCTL(val)	bfin_write32(SPI0_RXCTL, val)
    125. 

  125. #define bfin_read_SPI0_TXCTL()		bfin_read32(SPI0_TXCTL)
    126. 

  126. #define bfin_write_SPI0_TXCTL(val)	bfin_write32(SPI0_TXCTL, val)
    127. 

  127. #define bfin_read_SPI0_CLK()		bfin_read32(SPI0_CLK)
    128. 

  128. #define bfin_write_SPI0_CLK(val)	bfin_write32(SPI0_CLK, val)
    129. 

  129. #define bfin_read_SPI0_DLY()		bfin_read32(SPI0_DLY)
    130. 

  130. #define bfin_write_SPI0_DLY(val)	bfin_write32(SPI0_DLY, val)
    131. 

  131. #define bfin_read_SPI0_SLVSEL()		bfin_read32(SPI0_SLVSEL)
    132. 

  132. #define bfin_write_SPI0_SLVSEL(val)	bfin_write32(SPI0_SLVSEL, val)
    133. 

  133. #define bfin_read_SPI0_RWC()		bfin_read32(SPI0_RWC)
    134. 

  134. #define bfin_write_SPI0_RWC(val)	bfin_write32(SPI0_RWC, val)
    135. 

  135. #define bfin_read_SPI0_RWCR()		bfin_read32(SPI0_RWCR)
    136. 

  136. #define bfin_write_SPI0_RWCR(val)	bfin_write32(SPI0_RWCR, val)
    137. 

  137. #define bfin_read_SPI0_TWC()		bfin_read32(SPI0_TWC)
    138. 

  138. #define bfin_write_SPI0_TWC(val)	bfin_write32(SPI0_TWC, val)
    139. 

  139. #define bfin_read_SPI0_TWCR()		bfin_read32(SPI0_TWCR)
    140. 

  140. #define bfin_write_SPI0_TWCR(val)	bfin_write32(SPI0_TWCR, val)
    141. 

  141. #define bfin_read_SPI0_IMSK()		bfin_read32(SPI0_IMSK)
    142. 

  142. #define bfin_write_SPI0_IMSK(val)	bfin_write32(SPI0_IMSK, val)
    143. 

  143. #define bfin_read_SPI0_IMSK_CLR()	bfin_read32(SPI0_IMSK_CLR)
    144. 

  144. #define bfin_write_SPI0_IMSK_CLR(val)	bfin_write32(SPI0_IMSK_CLR, val)
    145. 

  145. #define bfin_read_SPI0_IMSK_SET()	bfin_read32(SPI0_IMSK_SET)
    146. 

  146. #define bfin_write_SPI0_IMSK_SET(val)	bfin_write32(SPI0_IMSK_SET, val)
    147. 

  147. #define bfin_read_SPI0_STAT()		bfin_read32(SPI0_STAT)
    148. 

  148. #define bfin_write_SPI0_STAT(val)	bfin_write32(SPI0_STAT, val)
    149. 

  149. #define bfin_read_SPI0_ILAT()		bfin_read32(SPI0_ILAT)
    150. 

  150. #define bfin_write_SPI0_ILAT(val)	bfin_write32(SPI0_ILAT, val)
    151. 

  151. #define bfin_read_SPI0_ILAT_CLR()	bfin_read32(SPI0_ILAT_CLR)
    152. 

  152. #define bfin_write_SPI0_ILAT_CLR(val)	bfin_write32(SPI0_ILAT_CLR, val)
    153. 

  153. #define bfin_read_SPI0_RFIFO()		bfin_read32(SPI0_RFIFO)
    154. 

  154. #define bfin_write_SPI0_RFIFO(val)	bfin_write32(SPI0_RFIFO, val)
    155. 

  155. #define bfin_read_SPI0_TFIFO()		bfin_read32(SPI0_TFIFO)
    156. 

  156. #define bfin_write_SPI0_TFIFO(val)	bfin_write32(SPI0_TFIFO, val)
    157. 

  157. 

  158. /* SPI1 Registers */
    159. 

  159. 

  160. #define bfin_read_SPI1_CTL()		bfin_read32(SPI1_CTL)
    161. 

  161. #define bfin_write_SPI1_CTL(val)	bfin_write32(SPI1_CTL, val)
    162. 

  162. #define bfin_read_SPI1_RXCTL()		bfin_read32(SPI1_RXCTL)
    163. 

  163. #define bfin_write_SPI1_RXCTL(val)	bfin_write32(SPI1_RXCTL, val)
    164. 

  164. #define bfin_read_SPI1_TXCTL()		bfin_read32(SPI1_TXCTL)
    165. 

  165. #define bfin_write_SPI1_TXCTL(val)	bfin_write32(SPI1_TXCTL, val)
    166. 

  166. #define bfin_read_SPI1_CLK()		bfin_read32(SPI1_CLK)
    167. 

  167. #define bfin_write_SPI1_CLK(val)	bfin_write32(SPI1_CLK, val)
    168. 

  168. #define bfin_read_SPI1_DLY()		bfin_read32(SPI1_DLY)
    169. 

  169. #define bfin_write_SPI1_DLY(val)	bfin_write32(SPI1_DLY, val)
    170. 

  170. #define bfin_read_SPI1_SLVSEL()		bfin_read32(SPI1_SLVSEL)
    171. 

  171. #define bfin_write_SPI1_SLVSEL(val)	bfin_write32(SPI1_SLVSEL, val)
    172. 

  172. #define bfin_read_SPI1_RWC()		bfin_read32(SPI1_RWC)
    173. 

  173. #define bfin_write_SPI1_RWC(val)	bfin_write32(SPI1_RWC, val)
    174. 

  174. #define bfin_read_SPI1_RWCR()		bfin_read32(SPI1_RWCR)
    175. 

  175. #define bfin_write_SPI1_RWCR(val)	bfin_write32(SPI1_RWCR, val)
    176. 

  176. #define bfin_read_SPI1_TWC()		bfin_read32(SPI1_TWC)
    177. 

  177. #define bfin_write_SPI1_TWC(val)	bfin_write32(SPI1_TWC, val)
    178. 

  178. #define bfin_read_SPI1_TWCR()		bfin_read32(SPI1_TWCR)
    179. 

  179. #define bfin_write_SPI1_TWCR(val)	bfin_write32(SPI1_TWCR, val)
    180. 

  180. #define bfin_read_SPI1_IMSK()		bfin_read32(SPI1_IMSK)
    181. 

  181. #define bfin_write_SPI1_IMSK(val)	bfin_write32(SPI1_IMSK, val)
    182. 

  182. #define bfin_read_SPI1_IMSK_CLR()	bfin_read32(SPI1_IMSK_CLR)
    183. 

  183. #define bfin_write_SPI1_IMSK_CLR(val)	bfin_write32(SPI1_IMSK_CLR, val)
    184. 

  184. #define bfin_read_SPI1_IMSK_SET()	bfin_read32(SPI1_IMSK_SET)
    185. 

  185. #define bfin_write_SPI1_IMSK_SET(val)	bfin_write32(SPI1_IMSK_SET, val)
    186. 

  186. #define bfin_read_SPI1_STAT()		bfin_read32(SPI1_STAT)
    187. 

  187. #define bfin_write_SPI1_STAT(val)	bfin_write32(SPI1_STAT, val)
    188. 

  188. #define bfin_read_SPI1_ILAT()		bfin_read32(SPI1_ILAT)
    189. 

  189. #define bfin_write_SPI1_ILAT(val)	bfin_write32(SPI1_ILAT, val)
    190. 

  190. #define bfin_read_SPI1_ILAT_CLR()	bfin_read32(SPI1_ILAT_CLR)
    191. 

  191. #define bfin_write_SPI1_ILAT_CLR(val)	bfin_write32(SPI1_ILAT_CLR, val)
    192. 

  192. #define bfin_read_SPI1_RFIFO()		bfin_read32(SPI1_RFIFO)
    193. 

  193. #define bfin_write_SPI1_RFIFO(val)	bfin_write32(SPI1_RFIFO, val)
    194. 

  194. #define bfin_read_SPI1_TFIFO()		bfin_read32(SPI1_TFIFO)
    195. 

  195. #define bfin_write_SPI1_TFIFO(val)	bfin_write32(SPI1_TFIFO, val)
    196. 

  196. 

  197. /* Timer 0-7 registers */
    198. 

  198. #define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
    199. 

  199. #define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG, val)
    200. 

  200. #define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
    201. 

  201. #define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER, val)
    202. 

  202. #define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
    203. 

  203. #define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD, val)
    204. 

  204. #define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
    205. 

  205. #define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH, val)
    206. 

  206. #define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
    207. 

  207. #define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG, val)
    208. 

  208. #define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
    209. 

  209. #define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER, val)
    210. 

  210. #define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
    211. 

  211. #define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD, val)
    212. 

  212. #define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
    213. 

  213. #define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH, val)
    214. 

  214. #define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
    215. 

  215. #define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG, val)
    216. 

  216. #define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
    217. 

  217. #define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER, val)
    218. 

  218. #define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
    219. 

  219. #define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD, val)
    220. 

  220. #define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
    221. 

  221. #define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH, val)
    222. 

  222. #define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
    223. 

  223. #define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG, val)
    224. 

  224. #define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
    225. 

  225. #define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER, val)
    226. 

  226. #define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
    227. 

  227. #define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD, val)
    228. 

  228. #define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
    229. 

  229. #define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH, val)
    230. 

  230. #define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
    231. 

  231. #define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG, val)
    232. 

  232. #define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
    233. 

  233. #define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER, val)
    234. 

  234. #define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
    235. 

  235. #define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD, val)
    236. 

  236. #define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
    237. 

  237. #define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH, val)
    238. 

  238. #define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
    239. 

  239. #define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG, val)
    240. 

  240. #define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
    241. 

  241. #define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER, val)
    242. 

  242. #define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
    243. 

  243. #define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD, val)
    244. 

  244. #define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
    245. 

  245. #define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH, val)
    246. 

  246. #define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
    247. 

  247. #define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG, val)
    248. 

  248. #define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
    249. 

  249. #define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER, val)
    250. 

  250. #define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
    251. 

  251. #define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD, val)
    252. 

  252. #define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
    253. 

  253. #define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH, val)
    254. 

  254. #define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
    255. 

  255. #define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG, val)
    256. 

  256. #define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
    257. 

  257. #define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER, val)
    258. 

  258. #define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
    259. 

  259. #define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD, val)
    260. 

  260. #define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
    261. 

  261. #define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH, val)
    262. 

  262. 

  263. 

  264. 

  265. 

  266. /* Two Wire Interface Registers (TWI0) */
    267. 

  267. 

  268. /* SPORT1 Registers */
    269. 

  269. 

  270. 

  271. /* SMC Registers */
    272. 

  272. #define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
    273. 

  273. #define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
    274. 

  274. #define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
    275. 

  275. #define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
    276. 

  276. #define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
    277. 

  277. #define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
    278. 

  278. #define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
    279. 

  279. #define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
    280. 

  280. #define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
    281. 

  281. #define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
    282. 

  282. #define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
    283. 

  283. #define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
    284. 

  284. #define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
    285. 

  285. #define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
    286. 

  286. #define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
    287. 

  287. #define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
    288. 

  288. #define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
    289. 

  289. #define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
    290. 

  290. #define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
    291. 

  291. #define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
    292. 

  292. #define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
    293. 

  293. #define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
    294. 

  294. #define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
    295. 

  295. #define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
    296. 

  296. #define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
    297. 

  297. #define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
    298. 

  298. #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
    299. 

  299. 

  300. /* DDR2 Memory Control Registers */
    301. 

  301. #define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
    302. 

  302. #define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
    303. 

  303. #define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
    304. 

  304. #define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
    305. 

  305. #define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
    306. 

  306. #define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
    307. 

  307. #define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
    308. 

  308. #define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
    309. 

  309. #define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
    310. 

  310. #define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
    311. 

  311. #define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
    312. 

  312. #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
    313. 

  313. #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
    314. 

  314. #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
    315. 

  315. #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
    316. 

  316. #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
    317. 

  317. #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
    318. 

  318. #define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
    319. 

  319. 

  320. /* DDR BankRead and Write Count Registers */
    321. 

  321. 

  322. 

  323. /* DMA Channel 0 Registers */
    324. 

  324. 

  325. #define bfin_read_DMA0_NEXT_DESC_PTR() 		bfin_read32(DMA0_NEXT_DESC_PTR)
    326. 

  326. #define bfin_write_DMA0_NEXT_DESC_PTR(val) 	bfin_write32(DMA0_NEXT_DESC_PTR, val)
    327. 

  327. #define bfin_read_DMA0_START_ADDR() 		bfin_read32(DMA0_START_ADDR)
    328. 

  328. #define bfin_write_DMA0_START_ADDR(val) 	bfin_write32(DMA0_START_ADDR, val)
    329. 

  329. #define bfin_read_DMA0_CONFIG()			bfin_read32(DMA0_CONFIG)
    330. 

  330. #define bfin_write_DMA0_CONFIG(val)		bfin_write32(DMA0_CONFIG, val)
    331. 

  331. #define bfin_read_DMA0_X_COUNT()		bfin_read32(DMA0_X_COUNT)
    332. 

  332. #define bfin_write_DMA0_X_COUNT(val)		bfin_write32(DMA0_X_COUNT, val)
    333. 

  333. #define bfin_read_DMA0_X_MODIFY()		bfin_read32(DMA0_X_MODIFY)
    334. 

  334. #define bfin_write_DMA0_X_MODIFY(val) 		bfin_write32(DMA0_X_MODIFY, val)
    335. 

  335. #define bfin_read_DMA0_Y_COUNT()		bfin_read32(DMA0_Y_COUNT)
    336. 

  336. #define bfin_write_DMA0_Y_COUNT(val)		bfin_write32(DMA0_Y_COUNT, val)
    337. 

  337. #define bfin_read_DMA0_Y_MODIFY()		bfin_read32(DMA0_Y_MODIFY)
    338. 

  338. #define bfin_write_DMA0_Y_MODIFY(val) 		bfin_write32(DMA0_Y_MODIFY, val)
    339. 

  339. #define bfin_read_DMA0_CURR_DESC_PTR() 		bfin_read32(DMA0_CURR_DESC_PTR)
    340. 

  340. #define bfin_write_DMA0_CURR_DESC_PTR(val) 	bfin_write32(DMA0_CURR_DESC_PTR, val)
    341. 

  341. #define bfin_read_DMA0_PREV_DESC_PTR() 		bfin_read32(DMA0_PREV_DESC_PTR)
    342. 

  342. #define bfin_write_DMA0_PREV_DESC_PTR(val) 	bfin_write32(DMA0_PREV_DESC_PTR, val)
    343. 

  343. #define bfin_read_DMA0_CURR_ADDR() 		bfin_read32(DMA0_CURR_ADDR)
    344. 

  344. #define bfin_write_DMA0_CURR_ADDR(val) 		bfin_write32(DMA0_CURR_ADDR, val)
    345. 

  345. #define bfin_read_DMA0_IRQ_STATUS()		bfin_read32(DMA0_IRQ_STATUS)
    346. 

  346. #define bfin_write_DMA0_IRQ_STATUS(val)		bfin_write32(DMA0_IRQ_STATUS, val)
    347. 

  347. #define bfin_read_DMA0_CURR_X_COUNT()		bfin_read32(DMA0_CURR_X_COUNT)
    348. 

  348. #define bfin_write_DMA0_CURR_X_COUNT(val)	bfin_write32(DMA0_CURR_X_COUNT, val)
    349. 

  349. #define bfin_read_DMA0_CURR_Y_COUNT()		bfin_read32(DMA0_CURR_Y_COUNT)
    350. 

  350. #define bfin_write_DMA0_CURR_Y_COUNT(val)	bfin_write32(DMA0_CURR_Y_COUNT, val)
    351. 

  351. #define bfin_read_DMA0_BWL_COUNT()		bfin_read32(DMA0_BWL_COUNT)
    352. 

  352. #define bfin_write_DMA0_BWL_COUNT(val)		bfin_write32(DMA0_BWL_COUNT, val)
    353. 

  353. #define bfin_read_DMA0_CURR_BWL_COUNT()		bfin_read32(DMA0_CURR_BWL_COUNT)
    354. 

  354. #define bfin_write_DMA0_CURR_BWL_COUNT(val)	bfin_write32(DMA0_CURR_BWL_COUNT, val)
    355. 

  355. #define bfin_read_DMA0_BWM_COUNT()		bfin_read32(DMA0_BWM_COUNT)
    356. 

  356. #define bfin_write_DMA0_BWM_COUNT(val)		bfin_write32(DMA0_BWM_COUNT, val)
    357. 

  357. #define bfin_read_DMA0_CURR_BWM_COUNT()		bfin_read32(DMA0_CURR_BWM_COUNT)
    358. 

  358. #define bfin_write_DMA0_CURR_BWM_COUNT(val)	bfin_write32(DMA0_CURR_BWM_COUNT, val)
    359. 

  359. 

  360. /* DMA Channel 1 Registers */
    361. 

  361. 

  362. #define bfin_read_DMA1_NEXT_DESC_PTR() 		bfin_read32(DMA1_NEXT_DESC_PTR)
    363. 

  363. #define bfin_write_DMA1_NEXT_DESC_PTR(val) 	bfin_write32(DMA1_NEXT_DESC_PTR, val)
    364. 

  364. #define bfin_read_DMA1_START_ADDR() 		bfin_read32(DMA1_START_ADDR)
    365. 

  365. #define bfin_write_DMA1_START_ADDR(val) 	bfin_write32(DMA1_START_ADDR, val)
    366. 

  366. #define bfin_read_DMA1_CONFIG()			bfin_read32(DMA1_CONFIG)
    367. 

  367. #define bfin_write_DMA1_CONFIG(val)		bfin_write32(DMA1_CONFIG, val)
    368. 

  368. #define bfin_read_DMA1_X_COUNT()		bfin_read32(DMA1_X_COUNT)
    369. 

  369. #define bfin_write_DMA1_X_COUNT(val)		bfin_write32(DMA1_X_COUNT, val)
    370. 

  370. #define bfin_read_DMA1_X_MODIFY()		bfin_read32(DMA1_X_MODIFY)
    371. 

  371. #define bfin_write_DMA1_X_MODIFY(val) 		bfin_write32(DMA1_X_MODIFY, val)
    372. 

  372. #define bfin_read_DMA1_Y_COUNT()		bfin_read32(DMA1_Y_COUNT)
    373. 

  373. #define bfin_write_DMA1_Y_COUNT(val)		bfin_write32(DMA1_Y_COUNT, val)
    374. 

  374. #define bfin_read_DMA1_Y_MODIFY()		bfin_read32(DMA1_Y_MODIFY)
    375. 

  375. #define bfin_write_DMA1_Y_MODIFY(val) 		bfin_write32(DMA1_Y_MODIFY, val)
    376. 

  376. #define bfin_read_DMA1_CURR_DESC_PTR() 		bfin_read32(DMA1_CURR_DESC_PTR)
    377. 

  377. #define bfin_write_DMA1_CURR_DESC_PTR(val) 	bfin_write32(DMA1_CURR_DESC_PTR, val)
    378. 

  378. #define bfin_read_DMA1_PREV_DESC_PTR() 		bfin_read32(DMA1_PREV_DESC_PTR)
    379. 

  379. #define bfin_write_DMA1_PREV_DESC_PTR(val) 	bfin_write32(DMA1_PREV_DESC_PTR, val)
    380. 

  380. #define bfin_read_DMA1_CURR_ADDR() 		bfin_read32(DMA1_CURR_ADDR)
    381. 

  381. #define bfin_write_DMA1_CURR_ADDR(val) 		bfin_write32(DMA1_CURR_ADDR, val)
    382. 

  382. #define bfin_read_DMA1_IRQ_STATUS()		bfin_read32(DMA1_IRQ_STATUS)
    383. 

  383. #define bfin_write_DMA1_IRQ_STATUS(val)		bfin_write32(DMA1_IRQ_STATUS, val)
    384. 

  384. #define bfin_read_DMA1_CURR_X_COUNT()		bfin_read32(DMA1_CURR_X_COUNT)
    385. 

  385. #define bfin_write_DMA1_CURR_X_COUNT(val)	bfin_write32(DMA1_CURR_X_COUNT, val)
    386. 

  386. #define bfin_read_DMA1_CURR_Y_COUNT()		bfin_read32(DMA1_CURR_Y_COUNT)
    387. 

  387. #define bfin_write_DMA1_CURR_Y_COUNT(val)	bfin_write32(DMA1_CURR_Y_COUNT, val)
    388. 

  388. #define bfin_read_DMA1_BWL_COUNT()		bfin_read32(DMA1_BWL_COUNT)
    389. 

  389. #define bfin_write_DMA1_BWL_COUNT(val)		bfin_write32(DMA1_BWL_COUNT, val)
    390. 

  390. #define bfin_read_DMA1_CURR_BWL_COUNT()		bfin_read32(DMA1_CURR_BWL_COUNT)
    391. 

  391. #define bfin_write_DMA1_CURR_BWL_COUNT(val)	bfin_write32(DMA1_CURR_BWL_COUNT, val)
    392. 

  392. #define bfin_read_DMA1_BWM_COUNT()		bfin_read32(DMA1_BWM_COUNT)
    393. 

  393. #define bfin_write_DMA1_BWM_COUNT(val)		bfin_write32(DMA1_BWM_COUNT, val)
    394. 

  394. #define bfin_read_DMA1_CURR_BWM_COUNT()		bfin_read32(DMA1_CURR_BWM_COUNT)
    395. 

  395. #define bfin_write_DMA1_CURR_BWM_COUNT(val)	bfin_write32(DMA1_CURR_BWM_COUNT, val)
    396. 

  396. 

  397. /* DMA Channel 2 Registers */
    398. 

  398. 

  399. #define bfin_read_DMA2_NEXT_DESC_PTR() 		bfin_read32(DMA2_NEXT_DESC_PTR)
    400. 

  400. #define bfin_write_DMA2_NEXT_DESC_PTR(val) 	bfin_write32(DMA2_NEXT_DESC_PTR, val)
    401. 

  401. #define bfin_read_DMA2_START_ADDR() 		bfin_read32(DMA2_START_ADDR)
    402. 

  402. #define bfin_write_DMA2_START_ADDR(val) 	bfin_write32(DMA2_START_ADDR, val)
    403. 

  403. #define bfin_read_DMA2_CONFIG()			bfin_read32(DMA2_CONFIG)
    404. 

  404. #define bfin_write_DMA2_CONFIG(val)		bfin_write32(DMA2_CONFIG, val)
    405. 

  405. #define bfin_read_DMA2_X_COUNT()		bfin_read32(DMA2_X_COUNT)
    406. 

  406. #define bfin_write_DMA2_X_COUNT(val)		bfin_write32(DMA2_X_COUNT, val)
    407. 

  407. #define bfin_read_DMA2_X_MODIFY()		bfin_read32(DMA2_X_MODIFY)
    408. 

  408. #define bfin_write_DMA2_X_MODIFY(val) 		bfin_write32(DMA2_X_MODIFY, val)
    409. 

  409. #define bfin_read_DMA2_Y_COUNT()		bfin_read32(DMA2_Y_COUNT)
    410. 

  410. #define bfin_write_DMA2_Y_COUNT(val)		bfin_write32(DMA2_Y_COUNT, val)
    411. 

  411. #define bfin_read_DMA2_Y_MODIFY()		bfin_read32(DMA2_Y_MODIFY)
    412. 

  412. #define bfin_write_DMA2_Y_MODIFY(val) 		bfin_write32(DMA2_Y_MODIFY, val)
    413. 

  413. #define bfin_read_DMA2_CURR_DESC_PTR() 		bfin_read32(DMA2_CURR_DESC_PTR)
    414. 

  414. #define bfin_write_DMA2_CURR_DESC_PTR(val) 	bfin_write32(DMA2_CURR_DESC_PTR, val)
    415. 

  415. #define bfin_read_DMA2_PREV_DESC_PTR() 		bfin_read32(DMA2_PREV_DESC_PTR)
    416. 

  416. #define bfin_write_DMA2_PREV_DESC_PTR(val) 	bfin_write32(DMA2_PREV_DESC_PTR, val)
    417. 

  417. #define bfin_read_DMA2_CURR_ADDR() 		bfin_read32(DMA2_CURR_ADDR)
    418. 

  418. #define bfin_write_DMA2_CURR_ADDR(val) 		bfin_write32(DMA2_CURR_ADDR, val)
    419. 

  419. #define bfin_read_DMA2_IRQ_STATUS()		bfin_read32(DMA2_IRQ_STATUS)
    420. 

  420. #define bfin_write_DMA2_IRQ_STATUS(val)		bfin_write32(DMA2_IRQ_STATUS, val)
    421. 

  421. #define bfin_read_DMA2_CURR_X_COUNT()		bfin_read32(DMA2_CURR_X_COUNT)
    422. 

  422. #define bfin_write_DMA2_CURR_X_COUNT(val)	bfin_write32(DMA2_CURR_X_COUNT, val)
    423. 

  423. #define bfin_read_DMA2_CURR_Y_COUNT()		bfin_read32(DMA2_CURR_Y_COUNT)
    424. 

  424. #define bfin_write_DMA2_CURR_Y_COUNT(val)	bfin_write32(DMA2_CURR_Y_COUNT, val)
    425. 

  425. #define bfin_read_DMA2_BWL_COUNT()		bfin_read32(DMA2_BWL_COUNT)
    426. 

  426. #define bfin_write_DMA2_BWL_COUNT(val)		bfin_write32(DMA2_BWL_COUNT, val)
    427. 

  427. #define bfin_read_DMA2_CURR_BWL_COUNT()		bfin_read32(DMA2_CURR_BWL_COUNT)
    428. 

  428. #define bfin_write_DMA2_CURR_BWL_COUNT(val)	bfin_write32(DMA2_CURR_BWL_COUNT, val)
    429. 

  429. #define bfin_read_DMA2_BWM_COUNT()		bfin_read32(DMA2_BWM_COUNT)
    430. 

  430. #define bfin_write_DMA2_BWM_COUNT(val)		bfin_write32(DMA2_BWM_COUNT, val)
    431. 

  431. #define bfin_read_DMA2_CURR_BWM_COUNT()		bfin_read32(DMA2_CURR_BWM_COUNT)
    432. 

  432. #define bfin_write_DMA2_CURR_BWM_COUNT(val)	bfin_write32(DMA2_CURR_BWM_COUNT, val)
    433. 

  433. 

  434. /* DMA Channel 3 Registers */
    435. 

  435. 

  436. #define bfin_read_DMA3_NEXT_DESC_PTR() 		bfin_read32(DMA3_NEXT_DESC_PTR)
    437. 

  437. #define bfin_write_DMA3_NEXT_DESC_PTR(val) 	bfin_write32(DMA3_NEXT_DESC_PTR, val)
    438. 

  438. #define bfin_read_DMA3_START_ADDR() 		bfin_read32(DMA3_START_ADDR)
    439. 

  439. #define bfin_write_DMA3_START_ADDR(val) 	bfin_write32(DMA3_START_ADDR, val)
    440. 

  440. #define bfin_read_DMA3_CONFIG()			bfin_read32(DMA3_CONFIG)
    441. 

  441. #define bfin_write_DMA3_CONFIG(val)		bfin_write32(DMA3_CONFIG, val)
    442. 

  442. #define bfin_read_DMA3_X_COUNT()		bfin_read32(DMA3_X_COUNT)
    443. 

  443. #define bfin_write_DMA3_X_COUNT(val)		bfin_write32(DMA3_X_COUNT, val)
    444. 

  444. #define bfin_read_DMA3_X_MODIFY()		bfin_read32(DMA3_X_MODIFY)
    445. 

  445. #define bfin_write_DMA3_X_MODIFY(val) 		bfin_write32(DMA3_X_MODIFY, val)
    446. 

  446. #define bfin_read_DMA3_Y_COUNT()		bfin_read32(DMA3_Y_COUNT)
    447. 

  447. #define bfin_write_DMA3_Y_COUNT(val)		bfin_write32(DMA3_Y_COUNT, val)
    448. 

  448. #define bfin_read_DMA3_Y_MODIFY()		bfin_read32(DMA3_Y_MODIFY)
    449. 

  449. #define bfin_write_DMA3_Y_MODIFY(val) 		bfin_write32(DMA3_Y_MODIFY, val)
    450. 

  450. #define bfin_read_DMA3_CURR_DESC_PTR() 		bfin_read32(DMA3_CURR_DESC_PTR)
    451. 

  451. #define bfin_write_DMA3_CURR_DESC_PTR(val) 	bfin_write32(DMA3_CURR_DESC_PTR, val)
    452. 

  452. #define bfin_read_DMA3_PREV_DESC_PTR() 		bfin_read32(DMA3_PREV_DESC_PTR)
    453. 

  453. #define bfin_write_DMA3_PREV_DESC_PTR(val) 	bfin_write32(DMA3_PREV_DESC_PTR, val)
    454. 

  454. #define bfin_read_DMA3_CURR_ADDR() 		bfin_read32(DMA3_CURR_ADDR)
    455. 

  455. #define bfin_write_DMA3_CURR_ADDR(val) 		bfin_write32(DMA3_CURR_ADDR, val)
    456. 

  456. #define bfin_read_DMA3_IRQ_STATUS()		bfin_read32(DMA3_IRQ_STATUS)
    457. 

  457. #define bfin_write_DMA3_IRQ_STATUS(val)		bfin_write32(DMA3_IRQ_STATUS, val)
    458. 

  458. #define bfin_read_DMA3_CURR_X_COUNT()		bfin_read32(DMA3_CURR_X_COUNT)
    459. 

  459. #define bfin_write_DMA3_CURR_X_COUNT(val)	bfin_write32(DMA3_CURR_X_COUNT, val)
    460. 

  460. #define bfin_read_DMA3_CURR_Y_COUNT()		bfin_read32(DMA3_CURR_Y_COUNT)
    461. 

  461. #define bfin_write_DMA3_CURR_Y_COUNT(val)	bfin_write32(DMA3_CURR_Y_COUNT, val)
    462. 

  462. #define bfin_read_DMA3_BWL_COUNT()		bfin_read32(DMA3_BWL_COUNT)
    463. 

  463. #define bfin_write_DMA3_BWL_COUNT(val)		bfin_write32(DMA3_BWL_COUNT, val)
    464. 

  464. #define bfin_read_DMA3_CURR_BWL_COUNT()		bfin_read32(DMA3_CURR_BWL_COUNT)
    465. 

  465. #define bfin_write_DMA3_CURR_BWL_COUNT(val)	bfin_write32(DMA3_CURR_BWL_COUNT, val)
    466. 

  466. #define bfin_read_DMA3_BWM_COUNT()		bfin_read32(DMA3_BWM_COUNT)
    467. 

  467. #define bfin_write_DMA3_BWM_COUNT(val)		bfin_write32(DMA3_BWM_COUNT, val)
    468. 

  468. #define bfin_read_DMA3_CURR_BWM_COUNT()		bfin_read32(DMA3_CURR_BWM_COUNT)
    469. 

  469. #define bfin_write_DMA3_CURR_BWM_COUNT(val)	bfin_write32(DMA3_CURR_BWM_COUNT, val)
    470. 

  470. 

  471. /* DMA Channel 4 Registers */
    472. 

  472. 

  473. #define bfin_read_DMA4_NEXT_DESC_PTR() 		bfin_read32(DMA4_NEXT_DESC_PTR)
    474. 

  474. #define bfin_write_DMA4_NEXT_DESC_PTR(val) 	bfin_write32(DMA4_NEXT_DESC_PTR, val)
    475. 

  475. #define bfin_read_DMA4_START_ADDR() 		bfin_read32(DMA4_START_ADDR)
    476. 

  476. #define bfin_write_DMA4_START_ADDR(val) 	bfin_write32(DMA4_START_ADDR, val)
    477. 

  477. #define bfin_read_DMA4_CONFIG()			bfin_read32(DMA4_CONFIG)
    478. 

  478. #define bfin_write_DMA4_CONFIG(val)		bfin_write32(DMA4_CONFIG, val)
    479. 

  479. #define bfin_read_DMA4_X_COUNT()		bfin_read32(DMA4_X_COUNT)
    480. 

  480. #define bfin_write_DMA4_X_COUNT(val)		bfin_write32(DMA4_X_COUNT, val)
    481. 

  481. #define bfin_read_DMA4_X_MODIFY()		bfin_read32(DMA4_X_MODIFY)
    482. 

  482. #define bfin_write_DMA4_X_MODIFY(val) 		bfin_write32(DMA4_X_MODIFY, val)
    483. 

  483. #define bfin_read_DMA4_Y_COUNT()		bfin_read32(DMA4_Y_COUNT)
    484. 

  484. #define bfin_write_DMA4_Y_COUNT(val)		bfin_write32(DMA4_Y_COUNT, val)
    485. 

  485. #define bfin_read_DMA4_Y_MODIFY()		bfin_read32(DMA4_Y_MODIFY)
    486. 

  486. #define bfin_write_DMA4_Y_MODIFY(val) 		bfin_write32(DMA4_Y_MODIFY, val)
    487. 

  487. #define bfin_read_DMA4_CURR_DESC_PTR() 		bfin_read32(DMA4_CURR_DESC_PTR)
    488. 

  488. #define bfin_write_DMA4_CURR_DESC_PTR(val) 	bfin_write32(DMA4_CURR_DESC_PTR, val)
    489. 

  489. #define bfin_read_DMA4_PREV_DESC_PTR() 		bfin_read32(DMA4_PREV_DESC_PTR)
    490. 

  490. #define bfin_write_DMA4_PREV_DESC_PTR(val) 	bfin_write32(DMA4_PREV_DESC_PTR, val)
    491. 

  491. #define bfin_read_DMA4_CURR_ADDR() 		bfin_read32(DMA4_CURR_ADDR)
    492. 

  492. #define bfin_write_DMA4_CURR_ADDR(val) 		bfin_write32(DMA4_CURR_ADDR, val)
    493. 

  493. #define bfin_read_DMA4_IRQ_STATUS()		bfin_read32(DMA4_IRQ_STATUS)
    494. 

  494. #define bfin_write_DMA4_IRQ_STATUS(val)		bfin_write32(DMA4_IRQ_STATUS, val)
    495. 

  495. #define bfin_read_DMA4_CURR_X_COUNT()		bfin_read32(DMA4_CURR_X_COUNT)
    496. 

  496. #define bfin_write_DMA4_CURR_X_COUNT(val)	bfin_write32(DMA4_CURR_X_COUNT, val)
    497. 

  497. #define bfin_read_DMA4_CURR_Y_COUNT()		bfin_read32(DMA4_CURR_Y_COUNT)
    498. 

  498. #define bfin_write_DMA4_CURR_Y_COUNT(val)	bfin_write32(DMA4_CURR_Y_COUNT, val)
    499. 

  499. #define bfin_read_DMA4_BWL_COUNT()		bfin_read32(DMA4_BWL_COUNT)
    500. 

  500. #define bfin_write_DMA4_BWL_COUNT(val)		bfin_write32(DMA4_BWL_COUNT, val)
    501. 

  501. #define bfin_read_DMA4_CURR_BWL_COUNT()		bfin_read32(DMA4_CURR_BWL_COUNT)
    502. 

  502. #define bfin_write_DMA4_CURR_BWL_COUNT(val)	bfin_write32(DMA4_CURR_BWL_COUNT, val)
    503. 

  503. #define bfin_read_DMA4_BWM_COUNT()		bfin_read32(DMA4_BWM_COUNT)
    504. 

  504. #define bfin_write_DMA4_BWM_COUNT(val)		bfin_write32(DMA4_BWM_COUNT, val)
    505. 

  505. #define bfin_read_DMA4_CURR_BWM_COUNT()		bfin_read32(DMA4_CURR_BWM_COUNT)
    506. 

  506. #define bfin_write_DMA4_CURR_BWM_COUNT(val)	bfin_write32(DMA4_CURR_BWM_COUNT, val)
    507. 

  507. 

  508. /* DMA Channel 5 Registers */
    509. 

  509. 

  510. #define bfin_read_DMA5_NEXT_DESC_PTR() 		bfin_read32(DMA5_NEXT_DESC_PTR)
    511. 

  511. #define bfin_write_DMA5_NEXT_DESC_PTR(val) 	bfin_write32(DMA5_NEXT_DESC_PTR, val)
    512. 

  512. #define bfin_read_DMA5_START_ADDR() 		bfin_read32(DMA5_START_ADDR)
    513. 

  513. #define bfin_write_DMA5_START_ADDR(val) 	bfin_write32(DMA5_START_ADDR, val)
    514. 

  514. #define bfin_read_DMA5_CONFIG()			bfin_read32(DMA5_CONFIG)
    515. 

  515. #define bfin_write_DMA5_CONFIG(val)		bfin_write32(DMA5_CONFIG, val)
    516. 

  516. #define bfin_read_DMA5_X_COUNT()		bfin_read32(DMA5_X_COUNT)
    517. 

  517. #define bfin_write_DMA5_X_COUNT(val)		bfin_write32(DMA5_X_COUNT, val)
    518. 

  518. #define bfin_read_DMA5_X_MODIFY()		bfin_read32(DMA5_X_MODIFY)
    519. 

  519. #define bfin_write_DMA5_X_MODIFY(val) 		bfin_write32(DMA5_X_MODIFY, val)
    520. 

  520. #define bfin_read_DMA5_Y_COUNT()		bfin_read32(DMA5_Y_COUNT)
    521. 

  521. #define bfin_write_DMA5_Y_COUNT(val)		bfin_write32(DMA5_Y_COUNT, val)
    522. 

  522. #define bfin_read_DMA5_Y_MODIFY()		bfin_read32(DMA5_Y_MODIFY)
    523. 

  523. #define bfin_write_DMA5_Y_MODIFY(val) 		bfin_write32(DMA5_Y_MODIFY, val)
    524. 

  524. #define bfin_read_DMA5_CURR_DESC_PTR() 		bfin_read32(DMA5_CURR_DESC_PTR)
    525. 

  525. #define bfin_write_DMA5_CURR_DESC_PTR(val) 	bfin_write32(DMA5_CURR_DESC_PTR, val)
    526. 

  526. #define bfin_read_DMA5_PREV_DESC_PTR() 		bfin_read32(DMA5_PREV_DESC_PTR)
    527. 

  527. #define bfin_write_DMA5_PREV_DESC_PTR(val) 	bfin_write32(DMA5_PREV_DESC_PTR, val)
    528. 

  528. #define bfin_read_DMA5_CURR_ADDR() 		bfin_read32(DMA5_CURR_ADDR)
    529. 

  529. #define bfin_write_DMA5_CURR_ADDR(val) 		bfin_write32(DMA5_CURR_ADDR, val)
    530. 

  530. #define bfin_read_DMA5_IRQ_STATUS()		bfin_read32(DMA5_IRQ_STATUS)
    531. 

  531. #define bfin_write_DMA5_IRQ_STATUS(val)		bfin_write32(DMA5_IRQ_STATUS, val)
    532. 

  532. #define bfin_read_DMA5_CURR_X_COUNT()		bfin_read32(DMA5_CURR_X_COUNT)
    533. 

  533. #define bfin_write_DMA5_CURR_X_COUNT(val)	bfin_write32(DMA5_CURR_X_COUNT, val)
    534. 

  534. #define bfin_read_DMA5_CURR_Y_COUNT()		bfin_read32(DMA5_CURR_Y_COUNT)
    535. 

  535. #define bfin_write_DMA5_CURR_Y_COUNT(val)	bfin_write32(DMA5_CURR_Y_COUNT, val)
    536. 

  536. #define bfin_read_DMA5_BWL_COUNT()		bfin_read32(DMA5_BWL_COUNT)
    537. 

  537. #define bfin_write_DMA5_BWL_COUNT(val)		bfin_write32(DMA5_BWL_COUNT, val)
    538. 

  538. #define bfin_read_DMA5_CURR_BWL_COUNT()		bfin_read32(DMA5_CURR_BWL_COUNT)
    539. 

  539. #define bfin_write_DMA5_CURR_BWL_COUNT(val)	bfin_write32(DMA5_CURR_BWL_COUNT, val)
    540. 

  540. #define bfin_read_DMA5_BWM_COUNT()		bfin_read32(DMA5_BWM_COUNT)
    541. 

  541. #define bfin_write_DMA5_BWM_COUNT(val)		bfin_write32(DMA5_BWM_COUNT, val)
    542. 

  542. #define bfin_read_DMA5_CURR_BWM_COUNT()		bfin_read32(DMA5_CURR_BWM_COUNT)
    543. 

  543. #define bfin_write_DMA5_CURR_BWM_COUNT(val)	bfin_write32(DMA5_CURR_BWM_COUNT, val)
    544. 

  544. 

  545. /* DMA Channel 6 Registers */
    546. 

  546. 

  547. #define bfin_read_DMA6_NEXT_DESC_PTR() 		bfin_read32(DMA6_NEXT_DESC_PTR)
    548. 

  548. #define bfin_write_DMA6_NEXT_DESC_PTR(val) 	bfin_write32(DMA6_NEXT_DESC_PTR, val)
    549. 

  549. #define bfin_read_DMA6_START_ADDR() 		bfin_read32(DMA6_START_ADDR)
    550. 

  550. #define bfin_write_DMA6_START_ADDR(val) 	bfin_write32(DMA6_START_ADDR, val)
    551. 

  551. #define bfin_read_DMA6_CONFIG()			bfin_read32(DMA6_CONFIG)
    552. 

  552. #define bfin_write_DMA6_CONFIG(val)		bfin_write32(DMA6_CONFIG, val)
    553. 

  553. #define bfin_read_DMA6_X_COUNT()		bfin_read32(DMA6_X_COUNT)
    554. 

  554. #define bfin_write_DMA6_X_COUNT(val)		bfin_write32(DMA6_X_COUNT, val)
    555. 

  555. #define bfin_read_DMA6_X_MODIFY()		bfin_read32(DMA6_X_MODIFY)
    556. 

  556. #define bfin_write_DMA6_X_MODIFY(val) 		bfin_write32(DMA6_X_MODIFY, val)
    557. 

  557. #define bfin_read_DMA6_Y_COUNT()		bfin_read32(DMA6_Y_COUNT)
    558. 

  558. #define bfin_write_DMA6_Y_COUNT(val)		bfin_write32(DMA6_Y_COUNT, val)
    559. 

  559. #define bfin_read_DMA6_Y_MODIFY()		bfin_read32(DMA6_Y_MODIFY)
    560. 

  560. #define bfin_write_DMA6_Y_MODIFY(val) 		bfin_write32(DMA6_Y_MODIFY, val)
    561. 

  561. #define bfin_read_DMA6_CURR_DESC_PTR() 		bfin_read32(DMA6_CURR_DESC_PTR)
    562. 

  562. #define bfin_write_DMA6_CURR_DESC_PTR(val) 	bfin_write32(DMA6_CURR_DESC_PTR, val)
    563. 

  563. #define bfin_read_DMA6_PREV_DESC_PTR() 		bfin_read32(DMA6_PREV_DESC_PTR)
    564. 

  564. #define bfin_write_DMA6_PREV_DESC_PTR(val) 	bfin_write32(DMA6_PREV_DESC_PTR, val)
    565. 

  565. #define bfin_read_DMA6_CURR_ADDR() 		bfin_read32(DMA6_CURR_ADDR)
    566. 

  566. #define bfin_write_DMA6_CURR_ADDR(val) 		bfin_write32(DMA6_CURR_ADDR, val)
    567. 

  567. #define bfin_read_DMA6_IRQ_STATUS()		bfin_read32(DMA6_IRQ_STATUS)
    568. 

  568. #define bfin_write_DMA6_IRQ_STATUS(val)		bfin_write32(DMA6_IRQ_STATUS, val)
    569. 

  569. #define bfin_read_DMA6_CURR_X_COUNT()		bfin_read32(DMA6_CURR_X_COUNT)
    570. 

  570. #define bfin_write_DMA6_CURR_X_COUNT(val)	bfin_write32(DMA6_CURR_X_COUNT, val)
    571. 

  571. #define bfin_read_DMA6_CURR_Y_COUNT()		bfin_read32(DMA6_CURR_Y_COUNT)
    572. 

  572. #define bfin_write_DMA6_CURR_Y_COUNT(val)	bfin_write32(DMA6_CURR_Y_COUNT, val)
    573. 

  573. #define bfin_read_DMA6_BWL_COUNT()		bfin_read32(DMA6_BWL_COUNT)
    574. 

  574. #define bfin_write_DMA6_BWL_COUNT(val)		bfin_write32(DMA6_BWL_COUNT, val)
    575. 

  575. #define bfin_read_DMA6_CURR_BWL_COUNT()		bfin_read32(DMA6_CURR_BWL_COUNT)
    576. 

  576. #define bfin_write_DMA6_CURR_BWL_COUNT(val)	bfin_write32(DMA6_CURR_BWL_COUNT, val)
    577. 

  577. #define bfin_read_DMA6_BWM_COUNT()		bfin_read32(DMA6_BWM_COUNT)
    578. 

  578. #define bfin_write_DMA6_BWM_COUNT(val)		bfin_write32(DMA6_BWM_COUNT, val)
    579. 

  579. #define bfin_read_DMA6_CURR_BWM_COUNT()		bfin_read32(DMA6_CURR_BWM_COUNT)
    580. 

  580. #define bfin_write_DMA6_CURR_BWM_COUNT(val)	bfin_write32(DMA6_CURR_BWM_COUNT, val)
    581. 

  581. 

  582. /* DMA Channel 7 Registers */
    583. 

  583. 

  584. #define bfin_read_DMA7_NEXT_DESC_PTR() 		bfin_read32(DMA7_NEXT_DESC_PTR)
    585. 

  585. #define bfin_write_DMA7_NEXT_DESC_PTR(val) 	bfin_write32(DMA7_NEXT_DESC_PTR, val)
    586. 

  586. #define bfin_read_DMA7_START_ADDR() 		bfin_read32(DMA7_START_ADDR)
    587. 

  587. #define bfin_write_DMA7_START_ADDR(val) 	bfin_write32(DMA7_START_ADDR, val)
    588. 

  588. #define bfin_read_DMA7_CONFIG()			bfin_read32(DMA7_CONFIG)
    589. 

  589. #define bfin_write_DMA7_CONFIG(val)		bfin_write32(DMA7_CONFIG, val)
    590. 

  590. #define bfin_read_DMA7_X_COUNT()		bfin_read32(DMA7_X_COUNT)
    591. 

  591. #define bfin_write_DMA7_X_COUNT(val)		bfin_write32(DMA7_X_COUNT, val)
    592. 

  592. #define bfin_read_DMA7_X_MODIFY()		bfin_read32(DMA7_X_MODIFY)
    593. 

  593. #define bfin_write_DMA7_X_MODIFY(val) 		bfin_write32(DMA7_X_MODIFY, val)
    594. 

  594. #define bfin_read_DMA7_Y_COUNT()		bfin_read32(DMA7_Y_COUNT)
    595. 

  595. #define bfin_write_DMA7_Y_COUNT(val)		bfin_write32(DMA7_Y_COUNT, val)
    596. 

  596. #define bfin_read_DMA7_Y_MODIFY()		bfin_read32(DMA7_Y_MODIFY)
    597. 

  597. #define bfin_write_DMA7_Y_MODIFY(val) 		bfin_write32(DMA7_Y_MODIFY, val)
    598. 

  598. #define bfin_read_DMA7_CURR_DESC_PTR() 		bfin_read32(DMA7_CURR_DESC_PTR)
    599. 

  599. #define bfin_write_DMA7_CURR_DESC_PTR(val) 	bfin_write32(DMA7_CURR_DESC_PTR, val)
    600. 

  600. #define bfin_read_DMA7_PREV_DESC_PTR() 		bfin_read32(DMA7_PREV_DESC_PTR)
    601. 

  601. #define bfin_write_DMA7_PREV_DESC_PTR(val) 	bfin_write32(DMA7_PREV_DESC_PTR, val)
    602. 

  602. #define bfin_read_DMA7_CURR_ADDR() 		bfin_read32(DMA7_CURR_ADDR)
    603. 

  603. #define bfin_write_DMA7_CURR_ADDR(val) 		bfin_write32(DMA7_CURR_ADDR, val)
    604. 

  604. #define bfin_read_DMA7_IRQ_STATUS()		bfin_read32(DMA7_IRQ_STATUS)
    605. 

  605. #define bfin_write_DMA7_IRQ_STATUS(val)		bfin_write32(DMA7_IRQ_STATUS, val)
    606. 

  606. #define bfin_read_DMA7_CURR_X_COUNT()		bfin_read32(DMA7_CURR_X_COUNT)
    607. 

  607. #define bfin_write_DMA7_CURR_X_COUNT(val)	bfin_write32(DMA7_CURR_X_COUNT, val)
    608. 

  608. #define bfin_read_DMA7_CURR_Y_COUNT()		bfin_read32(DMA7_CURR_Y_COUNT)
    609. 

  609. #define bfin_write_DMA7_CURR_Y_COUNT(val)	bfin_write32(DMA7_CURR_Y_COUNT, val)
    610. 

  610. #define bfin_read_DMA7_BWL_COUNT()		bfin_read32(DMA7_BWL_COUNT)
    611. 

  611. #define bfin_write_DMA7_BWL_COUNT(val)		bfin_write32(DMA7_BWL_COUNT, val)
    612. 

  612. #define bfin_read_DMA7_CURR_BWL_COUNT()		bfin_read32(DMA7_CURR_BWL_COUNT)
    613. 

  613. #define bfin_write_DMA7_CURR_BWL_COUNT(val)	bfin_write32(DMA7_CURR_BWL_COUNT, val)
    614. 

  614. #define bfin_read_DMA7_BWM_COUNT()		bfin_read32(DMA7_BWM_COUNT)
    615. 

  615. #define bfin_write_DMA7_BWM_COUNT(val)		bfin_write32(DMA7_BWM_COUNT, val)
    616. 

  616. #define bfin_read_DMA7_CURR_BWM_COUNT()		bfin_read32(DMA7_CURR_BWM_COUNT)
    617. 

  617. #define bfin_write_DMA7_CURR_BWM_COUNT(val)	bfin_write32(DMA7_CURR_BWM_COUNT, val)
    618. 

  618. 

  619. /* DMA Channel 8 Registers */
    620. 

  620. 

  621. #define bfin_read_DMA8_NEXT_DESC_PTR() 		bfin_read32(DMA8_NEXT_DESC_PTR)
    622. 

  622. #define bfin_write_DMA8_NEXT_DESC_PTR(val) 	bfin_write32(DMA8_NEXT_DESC_PTR, val)
    623. 

  623. #define bfin_read_DMA8_START_ADDR() 		bfin_read32(DMA8_START_ADDR)
    624. 

  624. #define bfin_write_DMA8_START_ADDR(val) 	bfin_write32(DMA8_START_ADDR, val)
    625. 

  625. #define bfin_read_DMA8_CONFIG()			bfin_read32(DMA8_CONFIG)
    626. 

  626. #define bfin_write_DMA8_CONFIG(val)		bfin_write32(DMA8_CONFIG, val)
    627. 

  627. #define bfin_read_DMA8_X_COUNT()		bfin_read32(DMA8_X_COUNT)
    628. 

  628. #define bfin_write_DMA8_X_COUNT(val)		bfin_write32(DMA8_X_COUNT, val)
    629. 

  629. #define bfin_read_DMA8_X_MODIFY()		bfin_read32(DMA8_X_MODIFY)
    630. 

  630. #define bfin_write_DMA8_X_MODIFY(val) 		bfin_write32(DMA8_X_MODIFY, val)
    631. 

  631. #define bfin_read_DMA8_Y_COUNT()		bfin_read32(DMA8_Y_COUNT)
    632. 

  632. #define bfin_write_DMA8_Y_COUNT(val)		bfin_write32(DMA8_Y_COUNT, val)
    633. 

  633. #define bfin_read_DMA8_Y_MODIFY()		bfin_read32(DMA8_Y_MODIFY)
    634. 

  634. #define bfin_write_DMA8_Y_MODIFY(val) 		bfin_write32(DMA8_Y_MODIFY, val)
    635. 

  635. #define bfin_read_DMA8_CURR_DESC_PTR() 		bfin_read32(DMA8_CURR_DESC_PTR)
    636. 

  636. #define bfin_write_DMA8_CURR_DESC_PTR(val) 	bfin_write32(DMA8_CURR_DESC_PTR, val)
    637. 

  637. #define bfin_read_DMA8_PREV_DESC_PTR() 		bfin_read32(DMA8_PREV_DESC_PTR)
    638. 

  638. #define bfin_write_DMA8_PREV_DESC_PTR(val) 	bfin_write32(DMA8_PREV_DESC_PTR, val)
    639. 

  639. #define bfin_read_DMA8_CURR_ADDR() 		bfin_read32(DMA8_CURR_ADDR)
    640. 

  640. #define bfin_write_DMA8_CURR_ADDR(val) 		bfin_write32(DMA8_CURR_ADDR, val)
    641. 

  641. #define bfin_read_DMA8_IRQ_STATUS()		bfin_read32(DMA8_IRQ_STATUS)
    642. 

  642. #define bfin_write_DMA8_IRQ_STATUS(val)		bfin_write32(DMA8_IRQ_STATUS, val)
    643. 

  643. #define bfin_read_DMA8_CURR_X_COUNT()		bfin_read32(DMA8_CURR_X_COUNT)
    644. 

  644. #define bfin_write_DMA8_CURR_X_COUNT(val)	bfin_write32(DMA8_CURR_X_COUNT, val)
    645. 

  645. #define bfin_read_DMA8_CURR_Y_COUNT()		bfin_read32(DMA8_CURR_Y_COUNT)
    646. 

  646. #define bfin_write_DMA8_CURR_Y_COUNT(val)	bfin_write32(DMA8_CURR_Y_COUNT, val)
    647. 

  647. #define bfin_read_DMA8_BWL_COUNT()		bfin_read32(DMA8_BWL_COUNT)
    648. 

  648. #define bfin_write_DMA8_BWL_COUNT(val)		bfin_write32(DMA8_BWL_COUNT, val)
    649. 

  649. #define bfin_read_DMA8_CURR_BWL_COUNT()		bfin_read32(DMA8_CURR_BWL_COUNT)
    650. 

  650. #define bfin_write_DMA8_CURR_BWL_COUNT(val)	bfin_write32(DMA8_CURR_BWL_COUNT, val)
    651. 

  651. #define bfin_read_DMA8_BWM_COUNT()		bfin_read32(DMA8_BWM_COUNT)
    652. 

  652. #define bfin_write_DMA8_BWM_COUNT(val)		bfin_write32(DMA8_BWM_COUNT, val)
    653. 

  653. #define bfin_read_DMA8_CURR_BWM_COUNT()		bfin_read32(DMA8_CURR_BWM_COUNT)
    654. 

  654. #define bfin_write_DMA8_CURR_BWM_COUNT(val)	bfin_write32(DMA8_CURR_BWM_COUNT, val)
    655. 

  655. 

  656. /* DMA Channel 9 Registers */
    657. 

  657. 

  658. #define bfin_read_DMA9_NEXT_DESC_PTR() 		bfin_read32(DMA9_NEXT_DESC_PTR)
    659. 

  659. #define bfin_write_DMA9_NEXT_DESC_PTR(val) 	bfin_write32(DMA9_NEXT_DESC_PTR, val)
    660. 

  660. #define bfin_read_DMA9_START_ADDR() 		bfin_read32(DMA9_START_ADDR)
    661. 

  661. #define bfin_write_DMA9_START_ADDR(val) 	bfin_write32(DMA9_START_ADDR, val)
    662. 

  662. #define bfin_read_DMA9_CONFIG()			bfin_read32(DMA9_CONFIG)
    663. 

  663. #define bfin_write_DMA9_CONFIG(val)		bfin_write32(DMA9_CONFIG, val)
    664. 

  664. #define bfin_read_DMA9_X_COUNT()		bfin_read32(DMA9_X_COUNT)
    665. 

  665. #define bfin_write_DMA9_X_COUNT(val)		bfin_write32(DMA9_X_COUNT, val)
    666. 

  666. #define bfin_read_DMA9_X_MODIFY()		bfin_read32(DMA9_X_MODIFY)
    667. 

  667. #define bfin_write_DMA9_X_MODIFY(val) 		bfin_write32(DMA9_X_MODIFY, val)
    668. 

  668. #define bfin_read_DMA9_Y_COUNT()		bfin_read32(DMA9_Y_COUNT)
    669. 

  669. #define bfin_write_DMA9_Y_COUNT(val)		bfin_write32(DMA9_Y_COUNT, val)
    670. 

  670. #define bfin_read_DMA9_Y_MODIFY()		bfin_read32(DMA9_Y_MODIFY)
    671. 

  671. #define bfin_write_DMA9_Y_MODIFY(val) 		bfin_write32(DMA9_Y_MODIFY, val)
    672. 

  672. #define bfin_read_DMA9_CURR_DESC_PTR() 		bfin_read32(DMA9_CURR_DESC_PTR)
    673. 

  673. #define bfin_write_DMA9_CURR_DESC_PTR(val) 	bfin_write32(DMA9_CURR_DESC_PTR, val)
    674. 

  674. #define bfin_read_DMA9_PREV_DESC_PTR() 		bfin_read32(DMA9_PREV_DESC_PTR)
    675. 

  675. #define bfin_write_DMA9_PREV_DESC_PTR(val) 	bfin_write32(DMA9_PREV_DESC_PTR, val)
    676. 

  676. #define bfin_read_DMA9_CURR_ADDR() 		bfin_read32(DMA9_CURR_ADDR)
    677. 

  677. #define bfin_write_DMA9_CURR_ADDR(val) 		bfin_write32(DMA9_CURR_ADDR, val)
    678. 

  678. #define bfin_read_DMA9_IRQ_STATUS()		bfin_read32(DMA9_IRQ_STATUS)
    679.