aiot/efDataDiscreteRateMining/databaseOperation/rtuTemperatureAndHumidityDataOperation.h

/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
 *
 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
 *	http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * S3C2410 GPIO register definitions
*/


#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H

#include <mach/gpio-nrs.h>

#define S3C24XX_MISCCR		S3C24XX_GPIOREG2(0x80)

/* general configuration options */

#define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)	/* not available on A */
#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)	/* not available for all */
#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)	/* bank A => addr/cs/nand */
#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)	/* not available on A */

/* register address for the GPIO registers.
 * S3C24XX_GPIOREG2 is for the second set of registers in the
 * GPIO which move between s3c2410 and s3c2412 type systems */

#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)


/* configure GPIO ports A..G */

/* port A - S3C2410: 22bits, zero in bit X makes pin X output
 * 1 makes port special function, this is default
*/
#define S3C2410_GPACON	   S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT	   S3C2410_GPIOREG(0x04)

#define S3C2410_GPA0_ADDR0   (1<<0)
#define S3C2410_GPA1_ADDR16  (1<<1)
#define S3C2410_GPA2_ADDR17  (1<<2)
#define S3C2410_GPA3_ADDR18  (1<<3)
#define S3C2410_GPA4_ADDR19  (1<<4)
#define S3C2410_GPA5_ADDR20  (1<<5)
#define S3C2410_GPA6_ADDR21  (1<<6)
#define S3C2410_GPA7_ADDR22  (1<<7)
#define S3C2410_GPA8_ADDR23  (1<<8)
#define S3C2410_GPA9_ADDR24  (1<<9)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2410_GPA12_nGCS1  (1<<12)
#define S3C2410_GPA13_nGCS2  (1<<13)
#define S3C2410_GPA14_nGCS3  (1<<14)
#define S3C2410_GPA15_nGCS4  (1<<15)
#define S3C2410_GPA16_nGCS5  (1<<16)
#define S3C2410_GPA17_CLE    (1<<17)
#define S3C2410_GPA18_ALE    (1<<18)
#define S3C2410_GPA19_nFWE   (1<<19)
#define S3C2410_GPA20_nFRE   (1<<20)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22_nFCE   (1<<22)

/* 0x08 and 0x0c are reserved on S3C2410 */

/* S3C2410:
 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 *   00 = input, 01 = output, 10=special function, 11=reserved

 * bit 0,1 = pin 0, 2,3= pin 1...
 *
 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
*/

#define S3C2410_GPBCON	   S3C2410_GPIOREG(0x10)
#define S3C2410_GPBDAT	   S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP	   S3C2410_GPIOREG(0x18)

/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */

#define S3C2410_GPB0_TOUT0   (0x02 << 0)

#define S3C2410_GPB1_TOUT1   (0x02 << 2)

#define S3C2410_GPB2_TOUT2   (0x02 << 4)

#define S3C2410_GPB3_TOUT3   (0x02 << 6)

#define S3C2410_GPB4_TCLK0   (0x02 << 8)
#define S3C2410_GPB4_MASK    (0x03 << 8)

#define S3C2410_GPB5_nXBACK  (0x02 << 10)
#define S3C2443_GPB5_XBACK   (0x03 << 10)

#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
#define S3C2443_GPB6_XBREQ   (0x03 << 12)

#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1  (0x03 << 14)

#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)

#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0  (0x03 << 18)

#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)

#define S3C2410_GPB_PUPDIS(x)  (1<<(x))

/* Port C consits of 16 GPIO/Special function
 *
 * almost identical setup to port b, but the special functions are mostly
 * to do with the video system's sync/etc.
*/

#define S3C2410_GPCCON	   S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT	   S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP	   S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0_LEND	(0x02 << 0)
#define S3C2410_GPC1_VCLK	(0x02 << 2)
#define S3C2410_GPC2_VLINE	(0x02 << 4)
#define S3C2410_GPC3_VFRAME	(0x02 << 6)
#define S3C2410_GPC4_VM		(0x02 << 8)
#define S3C2410_GPC5_LCDVF0	(0x02 << 10)
#define S3C2410_GPC6_LCDVF1	(0x02 << 12)
#define S3C2410_GPC7_LCDVF2	(0x02 << 14)
#define S3C2410_GPC8_VD0	(0x02 << 16)
#define S3C2410_GPC9_VD1	(0x02 << 18)
#define S3C2410_GPC10_VD2	(0x02 << 20)
#define S3C2410_GPC11_VD3	(0x02 << 22)
#define S3C2410_GPC12_VD4	(0x02 << 24)
#define S3C2410_GPC13_VD5	(0x02 << 26)
#define S3C2410_GPC14_VD6	(0x02 << 28)
#define S3C2410_GPC15_VD7	(0x02 << 30)
#define S3C2410_GPC_PUPDIS(x)  (1<<(x))

/*
 * S3C2410: Port D consists of 16 GPIO/Special function
 *
 * almost identical setup to port b, but the special functions are mostly
 * to do with the video system's data.
 *
 * almost identical setup to port c
*/

#define S3C2410_GPDCON	   S3C2410_GPIOREG(0x30)
#define S3C2410_GPDDAT	   S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP	   S3C2410_GPIOREG(0x38)

#define S3C2410_GPD0_VD8	(0x02 << 0)
#define S3C2442_GPD0_nSPICS1	(0x03 << 0)

#define S3C2410_GPD1_VD9	(0x02 << 2)
#define S3C2442_GPD1_SPICLK1	(0x03 << 2)

#define S3C2410_GPD2_VD10	(0x02 << 4)

#define S3C2410_GPD3_VD11	(0x02 << 6)

#define S3C2410_GPD4_VD12	(0x02 << 8)

#define S3C2410_GPD5_VD13	(0x02 << 10)

#define S3C2410_GPD6_VD14	(0x02 << 12)

#define S3C2410_GPD7_VD15	(0x02 << 14)

#define S3C2410_GPD8_VD16	(0x02 << 16)
#define S3C2440_GPD8_SPIMISO1	(0x03 << 16)

#define S3C2410_GPD9_VD17	(0x02 << 18)
#define S3C2440_GPD9_SPIMOSI1	(0x03 << 18)

#define S3C2410_GPD10_VD18	(0x02 << 20)
#define S3C2440_GPD10_SPICLK1	(0x03 << 20)

#define S3C2410_GPD11_VD19	(0x02 << 22)

#define S3C2410_GPD12_VD20	(0x02 << 24)

#define S3C2410_GPD13_VD21	(0x02 << 26)

#define S3C2410_GPD14_VD22	(0x02 << 28)
#define S3C2410_GPD14_nSS1	(0x03 << 28)

#define S3C2410_GPD15_VD23	(0x02 << 30)
#define S3C2410_GPD15_nSS0	(0x03 << 30)

#define S3C2410_GPD_PUPDIS(x)  (1<<(x))

/* S3C2410:
 * Port E consists of 16 GPIO/Special function
 *
 * again, the same as port B, but dealing with I2S, SDI, and
 * more miscellaneous functions
 *
 * GPIO / interrupt inputs
*/

#define S3C2410_GPECON	   S3C2410_GPIOREG(0x40)
#define S3C2410_GPEDAT	   S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP	   S3C2410_GPIOREG(0x48)

#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
#define S3C2410_GPE0_MASK      (0x03 << 0)

#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
#define S3C2410_GPE1_MASK      (0x03 << 2)

#define S3C2410_GPE2_CDCLK     (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)

#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
#define S3C2443_GPE3_AC_SDI    (0x03 << 6)
#define S3C2410_GPE3_nSS0      (0x03 << 6)
#define S3C2410_GPE3_MASK      (0x03 << 6)

#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
#define S3C2443_GPE4_AC_SDO    (0x03 << 8)
#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
#define S3C2410_GPE4_MASK      (0x03 << 8)

#define S3C2410_GPE5_SDCLK     (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)