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synchronousMemoryDatabase.h

synchronousMemoryDatabase.h 6.6 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF512_H
    8. 

  8. #define _DEF_BF512_H
    9. 

  9. 

  10. /* ************************************************************** */
    11. 

  11. /*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
    12. 

  12. /* ************************************************************** */
    13. 

  13. 

  14. /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
    15. 

  15. #define PLL_CTL				0xFFC00000	/* PLL Control Register						*/
    16. 

  16. #define PLL_DIV				0xFFC00004	/* PLL Divide Register						*/
    17. 

  17. #define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register				*/
    18. 

  18. #define PLL_STAT			0xFFC0000C	/* PLL Status Register						*/
    19. 

  19. #define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register					*/
    20. 

  20. #define CHIPID				0xFFC00014	/* Device ID Register */
    21. 

  21. 

  22. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)								*/
    23. 

  23. #define SWRST				0xFFC00100	/* Software Reset Register					*/
    24. 

  24. #define SYSCR				0xFFC00104	/* System Configuration Register				*/
    25. 

  25. #define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register			*/
    26. 

  26. 

  27. #define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register					*/
    28. 

  28. #define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0				*/
    29. 

  29. #define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1				*/
    30. 

  30. #define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2				*/
    31. 

  31. #define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3				*/
    32. 

  32. #define SIC_ISR0			0xFFC00120	/* Interrupt Status Register					*/
    33. 

  33. #define SIC_IWR0			0xFFC00124	/* Interrupt Wakeup Register					*/
    34. 

  34. 

  35. /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
    36. 

  36. #define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
    37. 

  37. #define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
    38. 

  38. #define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
    39. 

  39. #define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
    40. 

  40. #define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
    41. 

  41. #define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
    42. 

  42. #define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
    43. 

  43. 

  44. 

  45. /* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
    46. 

  46. #define WDOG_CTL			0xFFC00200	/* Watchdog Control Register				*/
    47. 

  47. #define WDOG_CNT			0xFFC00204	/* Watchdog Count Register					*/
    48. 

  48. #define WDOG_STAT			0xFFC00208	/* Watchdog Status Register					*/
    49. 

  49. 

  50. 

  51. /* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
    52. 

  52. #define RTC_STAT			0xFFC00300	/* RTC Status Register						*/
    53. 

  53. #define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register			*/
    54. 

  54. #define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register			*/
    55. 

  55. #define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register				*/
    56. 

  56. #define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register					*/
    57. 

  57. #define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register			*/
    58. 

  58. #define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro		*/
    59. 

  59. 

  60. 

  61. /* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
    62. 

  62. #define UART0_THR			0xFFC00400	/* Transmit Holding register				*/
    63. 

  63. #define UART0_RBR			0xFFC00400	/* Receive Buffer register					*/
    64. 

  64. #define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)					*/
    65. 

  65. #define UART0_IER			0xFFC00404	/* Interrupt Enable Register				*/
    66. 

  66. #define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)				*/
    67. 

  67. #define UART0_IIR			0xFFC00408	/* Interrupt Identification Register		*/
    68. 

  68. #define UART0_LCR			0xFFC0040C	/* Line Control Register					*/
    69. 

  69. #define UART0_MCR			0xFFC00410	/* Modem Control Register					*/
    70. 

  70. #define UART0_LSR			0xFFC00414	/* Line Status Register						*/
    71. 

  71. #define UART0_MSR			0xFFC00418	/* Modem Status Register					*/
    72. 

  72. #define UART0_SCR			0xFFC0041C	/* SCR Scratch Register						*/
    73. 

  73. #define UART0_GCTL			0xFFC00424	/* Global Control Register					*/
    74. 

  74. 

  75. /* SPI0 Controller			(0xFFC00500 - 0xFFC005FF)							*/
    76. 

  76. #define SPI0_REGBASE			0xFFC00500
    77. 

  77. #define SPI0_CTL			0xFFC00500	/* SPI Control Register						*/
    78. 

  78. #define SPI0_FLG			0xFFC00504	/* SPI Flag register						*/
    79. 

  79. #define SPI0_STAT			0xFFC00508	/* SPI Status register						*/
    80. 

  80. #define SPI0_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register				*/
    81. 

  81. #define SPI0_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register				*/
    82. 

  82. #define SPI0_BAUD			0xFFC00514	/* SPI Baud rate Register					*/
    83. 

  83. #define SPI0_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register					*/
    84. 

  84. 

  85. /* SPI1 Controller			(0xFFC03400 - 0xFFC034FF)							*/
    86. 

  86. #define SPI1_REGBASE			0xFFC03400
    87. 

  87. #define SPI1_CTL			0xFFC03400	/* SPI Control Register						*/
    88. 

  88. #define SPI1_FLG			0xFFC03404	/* SPI Flag register						*/
    89. 

  89. #define SPI1_STAT			0xFFC03408	/* SPI Status register						*/
    90. 

  90. #define SPI1_TDBR			0xFFC0340C	/* SPI Transmit Data Buffer Register				*/
    91. 

  91. #define SPI1_RDBR			0xFFC03410	/* SPI Receive Data Buffer Register				*/
    92. 

  92. #define SPI1_BAUD			0xFFC03414	/* SPI Baud rate Register					*/
    93. 

  93. #define SPI1_SHADOW			0xFFC03418	/* SPI_RDBR Shadow Register					*/
    94. 

  94. 

  95. /* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
    96. 

  96. #define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register			*/
    97. 

  97. #define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register					*/
    98. 

  98. #define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register					*/
    99. 

  99. #define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register					*/
    100. 

  100. 

  101. #define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register  			*/
    102. 

  102. #define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register        			*/
    103. 

  103. #define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register         			*/
    104. 

  104. #define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register          			*/
    105. 

  105. 

  106. #define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register  			*/
    107. 

  107. #define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register        			*/
    108. 

  108. #define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register         			*/
    109. 

  109. #define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register          			*/
    110. 

  110. 

  111. #define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register			*/
    112. 

  112. #define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register					*/
    113. 

  113. #define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register					*/
    114. 

  114. #define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register					*/
    115. 

  115. 

  116. #define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register  			*/
    117. 

  117. #define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register        			*/
    118. 

  118. #define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register         			*/
    119. 

  119. #define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register          			*/
    120. 

  120. 

  121. #define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register  			*/
    122. 

  122. #define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register        			*/
    123. 

  123. #define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register         			*/
    124.