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realizationOfDataCalculation.h

realizationOfDataCalculation.h 6.8 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
    3. 

  3.  *
    4. 

  4.  * Register definitions for IXP4xx chipset. This file contains 
    5. 

  5.  * register location and bit definitions only. Platform specific 
    6. 

  6.  * definitions and helper function declarations are in platform.h 
    7. 

  7.  * and machine-name.h.
    8. 

  8.  *
    9. 

  9.  * Copyright (C) 2002 Intel Corporation.
    10. 

  10.  * Copyright (C) 2003-2004 MontaVista Software, Inc.
    11. 

  11.  *
    12. 

  12.  * This program is free software; you can redistribute it and/or modify
    13. 

  13.  * it under the terms of the GNU General Public License version 2 as
    14. 

  14.  * published by the Free Software Foundation.
    15. 

  15.  *
    16. 

  16.  */
    17. 

  17. 

  18. #ifndef _ASM_ARM_IXP4XX_H_
    19. 

  19. #define _ASM_ARM_IXP4XX_H_
    20. 

  20. 

  21. /*
    22. 

  22.  * IXP4xx Linux Memory Map:
    23. 

  23.  *
    24. 

  24.  * Phy		Size		Virt		Description
    25. 

  25.  * =========================================================================
    26. 

  26.  *
    27. 

  27.  * 0x00000000	0x10000000(max)	PAGE_OFFSET	System RAM
    28. 

  28.  *
    29. 

  29.  * 0x48000000	0x04000000	ioremap'd	PCI Memory Space
    30. 

  30.  *
    31. 

  31.  * 0x50000000	0x10000000	ioremap'd	EXP BUS
    32. 

  32.  *
    33. 

  33.  * 0xC8000000	0x00013000	0xFEF00000	On-Chip Peripherals
    34. 

  34.  *
    35. 

  35.  * 0xC0000000	0x00001000	0xFEF13000	PCI CFG
    36. 

  36.  *
    37. 

  37.  * 0xC4000000	0x00001000	0xFEF14000	EXP CFG
    38. 

  38.  *
    39. 

  39.  * 0x60000000	0x00004000	0xFEF15000	QMgr
    40. 

  40.  */
    41. 

  41. 

  42. /*
    43. 

  43.  * Queue Manager
    44. 

  44.  */
    45. 

  45. #define IXP4XX_QMGR_BASE_PHYS		0x60000000
    46. 

  46. #define IXP4XX_QMGR_BASE_VIRT		IOMEM(0xFEF15000)
    47. 

  47. #define IXP4XX_QMGR_REGION_SIZE		0x00004000
    48. 

  48. 

  49. /*
    50. 

  50.  * Peripheral space, including debug UART. Must be section-aligned so that
    51. 

  51.  * it can be used with the low-level debug code.
    52. 

  52.  */
    53. 

  53. #define IXP4XX_PERIPHERAL_BASE_PHYS	0xC8000000
    54. 

  54. #define IXP4XX_PERIPHERAL_BASE_VIRT	IOMEM(0xFEF00000)
    55. 

  55. #define IXP4XX_PERIPHERAL_REGION_SIZE	0x00013000
    56. 

  56. 

  57. /*
    58. 

  58.  * PCI Config registers
    59. 

  59.  */
    60. 

  60. #define IXP4XX_PCI_CFG_BASE_PHYS	0xC0000000
    61. 

  61. #define IXP4XX_PCI_CFG_BASE_VIRT	IOMEM(0xFEF13000)
    62. 

  62. #define IXP4XX_PCI_CFG_REGION_SIZE	0x00001000
    63. 

  63. 

  64. /*
    65. 

  65.  * Expansion BUS Configuration registers
    66. 

  66.  */
    67. 

  67. #define IXP4XX_EXP_CFG_BASE_PHYS	0xC4000000
    68. 

  68. #define IXP4XX_EXP_CFG_BASE_VIRT	0xFEF14000
    69. 

  69. #define IXP4XX_EXP_CFG_REGION_SIZE	0x00001000
    70. 

  70. 

  71. #define IXP4XX_EXP_CS0_OFFSET	0x00
    72. 

  72. #define IXP4XX_EXP_CS1_OFFSET   0x04
    73. 

  73. #define IXP4XX_EXP_CS2_OFFSET   0x08
    74. 

  74. #define IXP4XX_EXP_CS3_OFFSET   0x0C
    75. 

  75. #define IXP4XX_EXP_CS4_OFFSET   0x10
    76. 

  76. #define IXP4XX_EXP_CS5_OFFSET   0x14
    77. 

  77. #define IXP4XX_EXP_CS6_OFFSET   0x18
    78. 

  78. #define IXP4XX_EXP_CS7_OFFSET   0x1C
    79. 

  79. #define IXP4XX_EXP_CFG0_OFFSET	0x20
    80. 

  80. #define IXP4XX_EXP_CFG1_OFFSET	0x24
    81. 

  81. #define IXP4XX_EXP_CFG2_OFFSET	0x28
    82. 

  82. #define IXP4XX_EXP_CFG3_OFFSET	0x2C
    83. 

  83. 

  84. /*
    85. 

  85.  * Expansion Bus Controller registers.
    86. 

  86.  */
    87. 

  87. #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
    88. 

  88. 

  89. #define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
    90. 

  90. #define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
    91. 

  91. #define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 
    92. 

  92. #define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
    93. 

  93. #define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
    94. 

  94. #define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
    95. 

  95. #define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     
    96. 

  96. #define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
    97. 

  97. 

  98. #define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 
    99. 

  99. #define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 
    100. 

  100. #define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 
    101. 

  101. #define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
    102. 

  102. 

  103. 

  104. /*
    105. 

  105.  * Peripheral Space Register Region Base Addresses
    106. 

  106.  */
    107. 

  107. #define IXP4XX_UART1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
    108. 

  108. #define IXP4XX_UART2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
    109. 

  109. #define IXP4XX_PMU_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
    110. 

  110. #define IXP4XX_INTC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
    111. 

  111. #define IXP4XX_GPIO_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
    112. 

  112. #define IXP4XX_TIMER_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
    113. 

  113. #define IXP4XX_NPEA_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
    114. 

  114. #define IXP4XX_NPEB_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
    115. 

  115. #define IXP4XX_NPEC_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
    116. 

  116. #define IXP4XX_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
    117. 

  117. #define IXP4XX_EthC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
    118. 

  118. #define IXP4XX_USB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
    119. 

  119. /* ixp46X only */
    120. 

  120. #define IXP4XX_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
    121. 

  121. #define IXP4XX_EthB1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
    122. 

  122. #define IXP4XX_EthB2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
    123. 

  123. #define IXP4XX_EthB3_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
    124. 

  124. #define IXP4XX_TIMESYNC_BASE_PHYS	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
    125. 

  125. #define IXP4XX_I2C_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
    126. 

  126. #define IXP4XX_SSP_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
    127. 

  127. 

  128. 

  129. #define IXP4XX_UART1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
    130. 

  130. #define IXP4XX_UART2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
    131. 

  131. #define IXP4XX_PMU_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
    132. 

  132. #define IXP4XX_INTC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
    133. 

  133. #define IXP4XX_GPIO_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
    134. 

  134. #define IXP4XX_TIMER_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
    135. 

  135. #define IXP4XX_NPEA_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
    136. 

  136. #define IXP4XX_NPEB_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
    137. 

  137. #define IXP4XX_NPEC_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
    138. 

  138. #define IXP4XX_EthB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
    139. 

  139. #define IXP4XX_EthC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
    140. 

  140. #define IXP4XX_USB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
    141. 

  141. /* ixp46X only */
    142. 

  142. #define IXP4XX_EthA_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
    143. 

  143. #define IXP4XX_EthB1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
    144. 

  144. #define IXP4XX_EthB2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
    145. 

  145. #define IXP4XX_EthB3_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
    146. 

  146. #define IXP4XX_TIMESYNC_BASE_VIRT	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
    147. 

  147. #define IXP4XX_I2C_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
    148. 

  148. #define IXP4XX_SSP_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
    149. 

  149. 

  150. /*
    151. 

  151.  * Constants to make it easy to access  Interrupt Controller registers
    152. 

  152.  */
    153. 

  153. #define IXP4XX_ICPR_OFFSET	0x00 /* Interrupt Status */
    154. 

  154. #define IXP4XX_ICMR_OFFSET	0x04 /* Interrupt Enable */
    155. 

  155. #define IXP4XX_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
    156. 

  156. #define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
    157. 

  157. #define IXP4XX_ICFP_OFFSET	0x10 /* FIQ Status */
    158. 

  158. #define IXP4XX_ICHR_OFFSET	0x14 /* Interrupt Priority */
    159. 

  159. #define IXP4XX_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
    160. 

  160. #define IXP4XX_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
    161. 

  161. 

  162. /*
    163. 

  163.  * IXP465-only
    164. 

  164.  */
    165. 

  165. #define	IXP4XX_ICPR2_OFFSET	0x20 /* Interrupt Status 2 */
    166. 

  166. #define	IXP4XX_ICMR2_OFFSET	0x24 /* Interrupt Enable 2 */
    167. 

  167. #define	IXP4XX_ICLR2_OFFSET	0x28 /* Interrupt IRQ/FIQ Select 2 */
    168. 

  168. #define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
    169. 

  169. #define IXP4XX_ICFP2_OFFSET	0x30 /* FIQ Status */
    170.