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aiot
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efDataDiscreteRateMining
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externalListeningThread
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dataMonitoring.h

dataMonitoring.h 9.6 KB
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  1. /*
    2. 

  2.  *
    3. 

  3.  * arch/arm/mach-u300/include/mach/syscon.h
    4. 

  4.  *
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2008-2012 ST-Ericsson AB
    7. 

  7.  *
    8. 

  8.  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __MACH_SYSCON_H
    12. 

  12. #define __MACH_SYSCON_H
    13. 

  13. 

  14. /*
    15. 

  15.  * All register defines for SYSCON registers that concerns individual
    16. 

  16.  * block clocks and reset lines are registered here. This is because
    17. 

  17.  * we don't want any other file to try to fool around with this stuff.
    18. 

  18.  */
    19. 

  19. 

  20. /* APP side SYSCON registers */
    21. 

  21. /* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
    22. 

  22. /* CLK Control Register 16bit (R/W) */
    23. 

  23. #define U300_SYSCON_CCR						(0x0000)
    24. 

  24. #define U300_SYSCON_CCR_I2S1_USE_VCXO				(0x0040)
    25. 

  25. #define U300_SYSCON_CCR_I2S0_USE_VCXO				(0x0020)
    26. 

  26. #define U300_SYSCON_CCR_TURN_VCXO_ON				(0x0008)
    27. 

  27. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK			(0x0007)
    28. 

  28. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER		(0x04)
    29. 

  29. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW			(0x03)
    30. 

  30. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE		(0x02)
    31. 

  31. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH			(0x01)
    32. 

  32. #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST			(0x00)
    33. 

  33. /* CLK Status Register 16bit (R/W) */
    34. 

  34. #define U300_SYSCON_CSR						(0x0004)
    35. 

  35. #define U300_SYSCON_CSR_PLL208_LOCK_IND				(0x0002)
    36. 

  36. #define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
    37. 

  37. /* Reset lines for SLOW devices 16bit (R/W) */
    38. 

  38. #define U300_SYSCON_RSR						(0x0014)
    39. 

  39. #define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
    40. 

  40. #define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
    41. 

  41. #define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
    42. 

  42. #define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
    43. 

  43. #define U300_SYSCON_RSR_KEYPAD_RESET_EN				(0x0020)
    44. 

  44. #define U300_SYSCON_RSR_GPIO_RESET_EN				(0x0010)
    45. 

  45. #define U300_SYSCON_RSR_EH_RESET_EN				(0x0008)
    46. 

  46. #define U300_SYSCON_RSR_BTR_RESET_EN				(0x0004)
    47. 

  47. #define U300_SYSCON_RSR_UART_RESET_EN				(0x0002)
    48. 

  48. #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
    49. 

  49. /* Reset lines for FAST devices 16bit (R/W) */
    50. 

  50. #define U300_SYSCON_RFR						(0x0018)
    51. 

  51. #define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
    52. 

  52. #define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
    53. 

  53. #define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
    54. 

  54. #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
    55. 

  55. #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE			(0x0008)
    56. 

  56. #define U300_SYSCON_RFR_I2C1_RESET_ENABLE			(0x0004)
    57. 

  57. #define U300_SYSCON_RFR_I2C0_RESET_ENABLE			(0x0002)
    58. 

  58. #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
    59. 

  59. /* Reset lines for the rest of the peripherals 16bit (R/W) */
    60. 

  60. #define U300_SYSCON_RRR						(0x001c)
    61. 

  61. #define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
    62. 

  62. #define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
    63. 

  63. #define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
    64. 

  64. #define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
    65. 

  65. #define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
    66. 

  66. #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN			(0x0080)
    67. 

  67. #define U300_SYSCON_RRR_NANDIF_RESET_EN				(0x0040)
    68. 

  68. #define U300_SYSCON_RRR_EMIF_RESET_EN				(0x0020)
    69. 

  69. #define U300_SYSCON_RRR_DMAC_RESET_EN				(0x0010)
    70. 

  70. #define U300_SYSCON_RRR_CPU_RESET_EN				(0x0008)
    71. 

  71. #define U300_SYSCON_RRR_APEX_RESET_EN				(0x0004)
    72. 

  72. #define U300_SYSCON_RRR_AHB_RESET_EN				(0x0002)
    73. 

  73. #define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
    74. 

  74. /* Clock enable for SLOW peripherals 16bit (R/W) */
    75. 

  75. #define U300_SYSCON_CESR					(0x0020)
    76. 

  76. #define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
    77. 

  77. #define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
    78. 

  78. #define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
    79. 

  79. #define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
    80. 

  80. #define U300_SYSCON_CESR_GPIO_CLK_EN				(0x0010)
    81. 

  81. #define U300_SYSCON_CESR_EH_CLK_EN				(0x0008)
    82. 

  82. #define U300_SYSCON_CESR_BTR_CLK_EN				(0x0004)
    83. 

  83. #define U300_SYSCON_CESR_UART_CLK_EN				(0x0002)
    84. 

  84. #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
    85. 

  85. /* Clock enable for FAST peripherals 16bit (R/W) */
    86. 

  86. #define U300_SYSCON_CEFR					(0x0024)
    87. 

  87. #define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
    88. 

  88. #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
    89. 

  89. #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
    90. 

  90. #define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
    91. 

  91. #define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
    92. 

  92. #define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
    93. 

  93. #define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
    94. 

  94. #define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
    95. 

  95. #define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
    96. 

  96. #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
    97. 

  97. /* Clock enable for the rest of the peripherals 16bit (R/W) */
    98. 

  98. #define U300_SYSCON_CERR					(0x0028)
    99. 

  99. #define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
    100. 

  100. #define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
    101. 

  101. #define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
    102. 

  102. #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
    103. 

  103. #define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
    104. 

  104. #define U300_SYSCON_CERR_XGAM_CLK_EN				(0x0100)
    105. 

  105. #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN			(0x0080)
    106. 

  106. #define U300_SYSCON_CERR_NANDIF_CLK_EN				(0x0040)
    107. 

  107. #define U300_SYSCON_CERR_EMIF_CLK_EN				(0x0020)
    108. 

  108. #define U300_SYSCON_CERR_DMAC_CLK_EN				(0x0010)
    109. 

  109. #define U300_SYSCON_CERR_CPU_CLK_EN				(0x0008)
    110. 

  110. #define U300_SYSCON_CERR_APEX_CLK_EN				(0x0004)
    111. 

  111. #define U300_SYSCON_CERR_AHB_CLK_EN				(0x0002)
    112. 

  112. #define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
    113. 

  113. /* Single block clock enable 16bit (-/W) */
    114. 

  114. #define U300_SYSCON_SBCER					(0x002c)
    115. 

  115. #define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
    116. 

  116. #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
    117. 

  117. #define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
    118. 

  118. #define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
    119. 

  119. #define U300_SYSCON_SBCER_GPIO_CLK_EN				(0x0004)
    120. 

  120. #define U300_SYSCON_SBCER_EH_CLK_EN				(0x0003)
    121. 

  121. #define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
    122. 

  122. #define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
    123. 

  123. #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
    124. 

  124. #define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
    125. 

  125. #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
    126. 

  126. #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
    127. 

  127. #define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
    128. 

  128. #define U300_SYSCON_SBCER_MMC_CLK_EN				(0x0015)
    129. 

  129. #define U300_SYSCON_SBCER_I2S1_CLK_EN				(0x0014)
    130. 

  130. #define U300_SYSCON_SBCER_I2S0_CLK_EN				(0x0013)
    131. 

  131. #define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
    132. 

  132. #define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
    133. 

  133. #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
    134. 

  134. #define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
    135. 

  135. #define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
    136. 

  136. #define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
    137. 

  137. #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
    138. 

  138. #define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
    139. 

  139. #define U300_SYSCON_SBCER_XGAM_CLK_EN				(0x0028)
    140. 

  140. #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN			(0x0027)
    141. 

  141. #define U300_SYSCON_SBCER_NANDIF_CLK_EN				(0x0026)
    142. 

  142. #define U300_SYSCON_SBCER_EMIF_CLK_EN				(0x0025)
    143. 

  143. #define U300_SYSCON_SBCER_DMAC_CLK_EN				(0x0024)
    144. 

  144. #define U300_SYSCON_SBCER_CPU_CLK_EN				(0x0023)
    145. 

  145. #define U300_SYSCON_SBCER_APEX_CLK_EN				(0x0022)
    146. 

  146. #define U300_SYSCON_SBCER_AHB_CLK_EN				(0x0021)
    147. 

  147. #define U300_SYSCON_SBCER_AAIF_CLK_EN				(0x0020)
    148. 

  148. /* Single block clock disable 16bit (-/W) */
    149. 

  149. #define U300_SYSCON_SBCDR					(0x0030)
    150. 

  150. /* Same values as above for SBCER */
    151. 

  151. /* Clock force SLOW peripherals 16bit (R/W) */
    152. 

  152. #define U300_SYSCON_CFSR					(0x003c)
    153. 

  153. #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
    154. 

  154. #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
    155. 

  155. #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
    156. 

  156. #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
    157. 

  157. #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN			(0x0010)
    158. 

  158. #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN			(0x0008)
    159. 

  159. #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN			(0x0004)
    160. 

  160. #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN			(0x0002)
    161. 

  161. #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN		(0x0001)
    162. 

  162. /* Clock force FAST peripherals 16bit (R/W) */
    163. 

  163. #define U300_SYSCON_CFFR					(0x40)
    164. 

  164. /* Values not defined. Define if you want to use them. */
    165. 

  165. /* Clock force the rest of the peripherals 16bit (R/W) */
    166. 

  166. #define U300_SYSCON_CFRR					(0x44)
    167. 

  167. #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
    168. 

  168. #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
    169. 

  169. #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
    170. 

  170. #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
    171. 

  171. #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
    172. 

  172. #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN			(0x0100)
    173. 

  173. #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN			(0x0080)
    174. 

  174. #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN			(0x0040)
    175. 

  175. #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN			(0x0020)
    176. 

  176. #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN			(0x0010)
    177. 

  177. #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN			(0x0008)
    178. 

  178. #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN			(0x0004)
    179. 

  179. #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN			(0x0002)
    180. 

  180. #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN			(0x0001)
    181. 

  181. /* PLL208 Frequency Control 16bit (R/W) */
    182. 

  182. #define U300_SYSCON_PFCR					(0x48)
    183. 

  183. #define U300_SYSCON_PFCR_DPLL_MULT_NUM				(0x000F)
    184. 

  184. /* Power Management Control 16bit (R/W) */
    185. 

  185. #define U300_SYSCON_PMCR					(0x50)
    186. 

  186. #define U300_SYSCON_PMCR_DCON_ENABLE				(0x0002)
    187. 

  187. #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE			(0x0001)
    188. 

  188. /*
    189. 

  189.  * All other clocking registers moved to clock.c!
    190. 

  190.  */
    191. 

  191. /* Reset Out 16bit (R/W) */
    192. 

  192. #define U300_SYSCON_RCR						(0x6c)
    193. 

  193. #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE			(0x0001)
    194. 

  194. /* EMIF Slew Rate Control 16bit (R/W) */
    195. 

  195. #define U300_SYSCON_SRCLR					(0x70)
    196. 

  196. #define U300_SYSCON_SRCLR_MASK					(0x03FF)
    197. 

  197. #define U300_SYSCON_SRCLR_VALUE					(0x03FF)
    198. 

  198. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B			(0x0200)
    199. 

  199. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A			(0x0100)
    200. 

  200. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B			(0x0080)
    201. 

  201. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A			(0x0040)
    202. 

  202. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B			(0x0020)
    203. 

  203. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A			(0x0010)
    204. 

  204. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B			(0x0008)
    205. 

  205. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A			(0x0004)
    206. 

  206. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B			(0x0002)
    207. 

  207. #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A			(0x0001)
    208. 

  208. /* EMIF Clock Control Register 16bit (R/W) */
    209. 

  209. #define U300_SYSCON_ECCR					(0x0078)
    210.