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rtuDataOperation.h

rtuDataOperation.h 9.9 KB
Riwayat Mentahan

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  1. #ifndef _M32102_H_
    2. 

  2. #define _M32102_H_
    3. 

  3. 

  4. /*
    5. 

  5.  * Renesas M32R 32102 group
    6. 

  6.  *
    7. 

  7.  * Copyright (c) 2001  Hitoshi Yamamoto
    8. 

  8.  * Copyright (c) 2003, 2004  Renesas Technology Corp.
    9. 

  9.  */
    10. 

  10. 

  11. /*======================================================================*
    12. 

  12.  * Special Function Register
    13. 

  13.  *======================================================================*/
    14. 

  14. #if !defined(CONFIG_CHIP_M32104)
    15. 

  15. #define M32R_SFR_OFFSET  (0x00E00000)  /* 0x00E00000-0x00EFFFFF 1[MB] */
    16. 

  16. #else
    17. 

  17. #define M32R_SFR_OFFSET  (0x00700000)  /* 0x00700000-0x007FFFFF 1[MB] */
    18. 

  18. #endif
    19. 

  19. 

  20. /*
    21. 

  21.  * Clock and Power Management registers.
    22. 

  22.  */
    23. 

  23. #define M32R_CPM_OFFSET          (0x000F4000+M32R_SFR_OFFSET)
    24. 

  24. 

  25. #define M32R_CPM_CPUCLKCR_PORTL  (0x00+M32R_CPM_OFFSET)
    26. 

  26. #define M32R_CPM_CLKMOD_PORTL    (0x04+M32R_CPM_OFFSET)
    27. 

  27. #define M32R_CPM_PLLCR_PORTL     (0x08+M32R_CPM_OFFSET)
    28. 

  28. 

  29. /*
    30. 

  30.  * DMA Controller registers.
    31. 

  31.  */
    32. 

  32. #define M32R_DMA_OFFSET		(0x000F8000+M32R_SFR_OFFSET)
    33. 

  33. 

  34. #define M32R_DMAEN_PORTL	(0x000+M32R_DMA_OFFSET)
    35. 

  35. #define M32R_DMAISTS_PORTL	(0x004+M32R_DMA_OFFSET)
    36. 

  36. #define M32R_DMAEDET_PORTL	(0x008+M32R_DMA_OFFSET)
    37. 

  37. #define M32R_DMAASTS_PORTL	(0x00c+M32R_DMA_OFFSET)
    38. 

  38. 

  39. #define M32R_DMA0CR0_PORTL	(0x100+M32R_DMA_OFFSET)
    40. 

  40. #define M32R_DMA0CR1_PORTL	(0x104+M32R_DMA_OFFSET)
    41. 

  41. #define M32R_DMA0CSA_PORTL	(0x108+M32R_DMA_OFFSET)
    42. 

  42. #define M32R_DMA0RSA_PORTL	(0x10c+M32R_DMA_OFFSET)
    43. 

  43. #define M32R_DMA0CDA_PORTL	(0x110+M32R_DMA_OFFSET)
    44. 

  44. #define M32R_DMA0RDA_PORTL	(0x114+M32R_DMA_OFFSET)
    45. 

  45. #define M32R_DMA0CBCUT_PORTL	(0x118+M32R_DMA_OFFSET)
    46. 

  46. #define M32R_DMA0RBCUT_PORTL	(0x11c+M32R_DMA_OFFSET)
    47. 

  47. 

  48. #define M32R_DMA1CR0_PORTL	(0x200+M32R_DMA_OFFSET)
    49. 

  49. #define M32R_DMA1CR1_PORTL	(0x204+M32R_DMA_OFFSET)
    50. 

  50. #define M32R_DMA1CSA_PORTL	(0x208+M32R_DMA_OFFSET)
    51. 

  51. #define M32R_DMA1RSA_PORTL	(0x20c+M32R_DMA_OFFSET)
    52. 

  52. #define M32R_DMA1CDA_PORTL	(0x210+M32R_DMA_OFFSET)
    53. 

  53. #define M32R_DMA1RDA_PORTL	(0x214+M32R_DMA_OFFSET)
    54. 

  54. #define M32R_DMA1CBCUT_PORTL	(0x218+M32R_DMA_OFFSET)
    55. 

  55. #define M32R_DMA1RBCUT_PORTL	(0x21c+M32R_DMA_OFFSET)
    56. 

  56. 

  57. /*
    58. 

  58.  * Multi Function Timer registers.
    59. 

  59.  */
    60. 

  60. #define M32R_MFT_OFFSET        (0x000FC000+M32R_SFR_OFFSET)
    61. 

  61. 

  62. #define M32R_MFTCR_PORTL       (0x000+M32R_MFT_OFFSET)  /* MFT control */
    63. 

  63. #define M32R_MFTRPR_PORTL      (0x004+M32R_MFT_OFFSET)  /* MFT real port */
    64. 

  64. 

  65. #define M32R_MFT0_OFFSET       (0x100+M32R_MFT_OFFSET)
    66. 

  66. #define M32R_MFT0MOD_PORTL     (0x00+M32R_MFT0_OFFSET)  /* MFT0 mode */
    67. 

  67. #define M32R_MFT0BOS_PORTL     (0x04+M32R_MFT0_OFFSET)  /* MFT0 b-port output status */
    68. 

  68. #define M32R_MFT0CUT_PORTL     (0x08+M32R_MFT0_OFFSET)  /* MFT0 count */
    69. 

  69. #define M32R_MFT0RLD_PORTL     (0x0C+M32R_MFT0_OFFSET)  /* MFT0 reload */
    70. 

  70. #define M32R_MFT0CMPRLD_PORTL  (0x10+M32R_MFT0_OFFSET)  /* MFT0 compare reload */
    71. 

  71. 

  72. #define M32R_MFT1_OFFSET       (0x200+M32R_MFT_OFFSET)
    73. 

  73. #define M32R_MFT1MOD_PORTL     (0x00+M32R_MFT1_OFFSET)  /* MFT1 mode */
    74. 

  74. #define M32R_MFT1BOS_PORTL     (0x04+M32R_MFT1_OFFSET)  /* MFT1 b-port output status */
    75. 

  75. #define M32R_MFT1CUT_PORTL     (0x08+M32R_MFT1_OFFSET)  /* MFT1 count */
    76. 

  76. #define M32R_MFT1RLD_PORTL     (0x0C+M32R_MFT1_OFFSET)  /* MFT1 reload */
    77. 

  77. #define M32R_MFT1CMPRLD_PORTL  (0x10+M32R_MFT1_OFFSET)  /* MFT1 compare reload */
    78. 

  78. 

  79. #define M32R_MFT2_OFFSET       (0x300+M32R_MFT_OFFSET)
    80. 

  80. #define M32R_MFT2MOD_PORTL     (0x00+M32R_MFT2_OFFSET)  /* MFT2 mode */
    81. 

  81. #define M32R_MFT2BOS_PORTL     (0x04+M32R_MFT2_OFFSET)  /* MFT2 b-port output status */
    82. 

  82. #define M32R_MFT2CUT_PORTL     (0x08+M32R_MFT2_OFFSET)  /* MFT2 count */
    83. 

  83. #define M32R_MFT2RLD_PORTL     (0x0C+M32R_MFT2_OFFSET)  /* MFT2 reload */
    84. 

  84. #define M32R_MFT2CMPRLD_PORTL  (0x10+M32R_MFT2_OFFSET)  /* MFT2 compare reload */
    85. 

  85. 

  86. #define M32R_MFT3_OFFSET       (0x400+M32R_MFT_OFFSET)
    87. 

  87. #define M32R_MFT3MOD_PORTL     (0x00+M32R_MFT3_OFFSET)  /* MFT3 mode */
    88. 

  88. #define M32R_MFT3BOS_PORTL     (0x04+M32R_MFT3_OFFSET)  /* MFT3 b-port output status */
    89. 

  89. #define M32R_MFT3CUT_PORTL     (0x08+M32R_MFT3_OFFSET)  /* MFT3 count */
    90. 

  90. #define M32R_MFT3RLD_PORTL     (0x0C+M32R_MFT3_OFFSET)  /* MFT3 reload */
    91. 

  91. #define M32R_MFT3CMPRLD_PORTL  (0x10+M32R_MFT3_OFFSET)  /* MFT3 compare reload */
    92. 

  92. 

  93. #define M32R_MFT4_OFFSET       (0x500+M32R_MFT_OFFSET)
    94. 

  94. #define M32R_MFT4MOD_PORTL     (0x00+M32R_MFT4_OFFSET)  /* MFT4 mode */
    95. 

  95. #define M32R_MFT4BOS_PORTL     (0x04+M32R_MFT4_OFFSET)  /* MFT4 b-port output status */
    96. 

  96. #define M32R_MFT4CUT_PORTL     (0x08+M32R_MFT4_OFFSET)  /* MFT4 count */
    97. 

  97. #define M32R_MFT4RLD_PORTL     (0x0C+M32R_MFT4_OFFSET)  /* MFT4 reload */
    98. 

  98. #define M32R_MFT4CMPRLD_PORTL  (0x10+M32R_MFT4_OFFSET)  /* MFT4 compare reload */
    99. 

  99. 

  100. #define M32R_MFT5_OFFSET       (0x600+M32R_MFT_OFFSET)
    101. 

  101. #define M32R_MFT5MOD_PORTL     (0x00+M32R_MFT5_OFFSET)  /* MFT4 mode */
    102. 

  102. #define M32R_MFT5BOS_PORTL     (0x04+M32R_MFT5_OFFSET)  /* MFT4 b-port output status */
    103. 

  103. #define M32R_MFT5CUT_PORTL     (0x08+M32R_MFT5_OFFSET)  /* MFT4 count */
    104. 

  104. #define M32R_MFT5RLD_PORTL     (0x0C+M32R_MFT5_OFFSET)  /* MFT4 reload */
    105. 

  105. #define M32R_MFT5CMPRLD_PORTL  (0x10+M32R_MFT5_OFFSET)  /* MFT4 compare reload */
    106. 

  106. 

  107. #if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
    108. 

  108. 	|| defined(CONFIG_CHIP_M32104)
    109. 

  109. #define M32R_MFTCR_MFT0MSK  (1UL<<31)  /* b0 */
    110. 

  110. #define M32R_MFTCR_MFT1MSK  (1UL<<30)  /* b1 */
    111. 

  111. #define M32R_MFTCR_MFT2MSK  (1UL<<29)  /* b2 */
    112. 

  112. #define M32R_MFTCR_MFT3MSK  (1UL<<28)  /* b3 */
    113. 

  113. #define M32R_MFTCR_MFT4MSK  (1UL<<27)  /* b4 */
    114. 

  114. #define M32R_MFTCR_MFT5MSK  (1UL<<26)  /* b5 */
    115. 

  115. #define M32R_MFTCR_MFT0EN   (1UL<<23)  /* b8 */
    116. 

  116. #define M32R_MFTCR_MFT1EN   (1UL<<22)  /* b9 */
    117. 

  117. #define M32R_MFTCR_MFT2EN   (1UL<<21)  /* b10 */
    118. 

  118. #define M32R_MFTCR_MFT3EN   (1UL<<20)  /* b11 */
    119. 

  119. #define M32R_MFTCR_MFT4EN   (1UL<<19)  /* b12 */
    120. 

  120. #define M32R_MFTCR_MFT5EN   (1UL<<18)  /* b13 */
    121. 

  121. #else
    122. 

  122. #define M32R_MFTCR_MFT0MSK  (1UL<<15)  /* b16 */
    123. 

  123. #define M32R_MFTCR_MFT1MSK  (1UL<<14)  /* b17 */
    124. 

  124. #define M32R_MFTCR_MFT2MSK  (1UL<<13)  /* b18 */
    125. 

  125. #define M32R_MFTCR_MFT3MSK  (1UL<<12)  /* b19 */
    126. 

  126. #define M32R_MFTCR_MFT4MSK  (1UL<<11)  /* b20 */
    127. 

  127. #define M32R_MFTCR_MFT5MSK  (1UL<<10)  /* b21 */
    128. 

  128. #define M32R_MFTCR_MFT0EN   (1UL<<7)   /* b24 */
    129. 

  129. #define M32R_MFTCR_MFT1EN   (1UL<<6)   /* b25 */
    130. 

  130. #define M32R_MFTCR_MFT2EN   (1UL<<5)   /* b26 */
    131. 

  131. #define M32R_MFTCR_MFT3EN   (1UL<<4)   /* b27 */
    132. 

  132. #define M32R_MFTCR_MFT4EN   (1UL<<3)   /* b28 */
    133. 

  133. #define M32R_MFTCR_MFT5EN   (1UL<<2)   /* b29 */
    134. 

  134. #endif
    135. 

  135. 

  136. #define M32R_MFTMOD_CC_MASK    (1UL<<15)  /* b16 */
    137. 

  137. #define M32R_MFTMOD_TCCR       (1UL<<13)  /* b18 */
    138. 

  138. #define M32R_MFTMOD_GTSEL000   (0UL<<8)   /* b21-23 : 000 */
    139. 

  139. #define M32R_MFTMOD_GTSEL001   (1UL<<8)   /* b21-23 : 001 */
    140. 

  140. #define M32R_MFTMOD_GTSEL010   (2UL<<8)   /* b21-23 : 010 */
    141. 

  141. #define M32R_MFTMOD_GTSEL011   (3UL<<8)   /* b21-23 : 011 */
    142. 

  142. #define M32R_MFTMOD_GTSEL110   (6UL<<8)   /* b21-23 : 110 */
    143. 

  143. #define M32R_MFTMOD_GTSEL111   (7UL<<8)   /* b21-23 : 111 */
    144. 

  144. #define M32R_MFTMOD_CMSEL      (1UL<<3)   /* b28 */
    145. 

  145. #define M32R_MFTMOD_CSSEL000   (0UL<<0)   /* b29-b31 : 000 */
    146. 

  146. #define M32R_MFTMOD_CSSEL001   (1UL<<0)   /* b29-b31 : 001 */
    147. 

  147. #define M32R_MFTMOD_CSSEL010   (2UL<<0)   /* b29-b31 : 010 */
    148. 

  148. #define M32R_MFTMOD_CSSEL011   (3UL<<0)   /* b29-b31 : 011 */
    149. 

  149. #define M32R_MFTMOD_CSSEL100   (4UL<<0)   /* b29-b31 : 100 */
    150. 

  150. #define M32R_MFTMOD_CSSEL110   (6UL<<0)   /* b29-b31 : 110 */
    151. 

  151. 

  152. /*
    153. 

  153.  * Serial I/O registers.
    154. 

  154.  */
    155. 

  155. #define M32R_SIO_OFFSET  (0x000FD000+M32R_SFR_OFFSET)
    156. 

  156. 

  157. #define M32R_SIO0_CR_PORTL    (0x000+M32R_SIO_OFFSET)
    158. 

  158. #define M32R_SIO0_MOD0_PORTL  (0x004+M32R_SIO_OFFSET)
    159. 

  159. #define M32R_SIO0_MOD1_PORTL  (0x008+M32R_SIO_OFFSET)
    160. 

  160. #define M32R_SIO0_STS_PORTL   (0x00C+M32R_SIO_OFFSET)
    161. 

  161. #define M32R_SIO0_TRCR_PORTL  (0x010+M32R_SIO_OFFSET)
    162. 

  162. #define M32R_SIO0_BAUR_PORTL  (0x014+M32R_SIO_OFFSET)
    163. 

  163. #define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
    164. 

  164. #define M32R_SIO0_TXB_PORTL   (0x01C+M32R_SIO_OFFSET)
    165. 

  165. #define M32R_SIO0_RXB_PORTL   (0x020+M32R_SIO_OFFSET)
    166. 

  166. 

  167. /*
    168. 

  168.  * Interrupt Control Unit registers.
    169. 

  169.  */
    170. 

  170. #define M32R_ICU_OFFSET       (0x000FF000+M32R_SFR_OFFSET)
    171. 

  171. #define M32R_ICU_ISTS_PORTL   (0x004+M32R_ICU_OFFSET)
    172. 

  172. #define M32R_ICU_IREQ0_PORTL  (0x008+M32R_ICU_OFFSET)
    173. 

  173. #define M32R_ICU_IREQ1_PORTL  (0x00C+M32R_ICU_OFFSET)
    174. 

  174. #define M32R_ICU_SBICR_PORTL  (0x018+M32R_ICU_OFFSET)
    175. 

  175. #define M32R_ICU_IMASK_PORTL  (0x01C+M32R_ICU_OFFSET)
    176. 

  176. #define M32R_ICU_CR1_PORTL    (0x200+M32R_ICU_OFFSET)  /* INT0 */
    177. 

  177. #define M32R_ICU_CR2_PORTL    (0x204+M32R_ICU_OFFSET)  /* INT1 */
    178. 

  178. #define M32R_ICU_CR3_PORTL    (0x208+M32R_ICU_OFFSET)  /* INT2 */
    179. 

  179. #define M32R_ICU_CR4_PORTL    (0x20C+M32R_ICU_OFFSET)  /* INT3 */
    180. 

  180. #define M32R_ICU_CR5_PORTL    (0x210+M32R_ICU_OFFSET)  /* INT4 */
    181. 

  181. #define M32R_ICU_CR6_PORTL    (0x214+M32R_ICU_OFFSET)  /* INT5 */
    182. 

  182. #define M32R_ICU_CR7_PORTL    (0x218+M32R_ICU_OFFSET)  /* INT6 */
    183. 

  183. #define M32R_ICU_CR8_PORTL    (0x219+M32R_ICU_OFFSET)  /* INT7 */
    184. 

  184. #define M32R_ICU_CR16_PORTL   (0x23C+M32R_ICU_OFFSET)  /* MFT0 */
    185. 

  185. #define M32R_ICU_CR17_PORTL   (0x240+M32R_ICU_OFFSET)  /* MFT1 */
    186. 

  186. #define M32R_ICU_CR18_PORTL   (0x244+M32R_ICU_OFFSET)  /* MFT2 */
    187. 

  187. #define M32R_ICU_CR19_PORTL   (0x248+M32R_ICU_OFFSET)  /* MFT3 */
    188. 

  188. #define M32R_ICU_CR20_PORTL   (0x24C+M32R_ICU_OFFSET)  /* MFT4 */
    189. 

  189. #define M32R_ICU_CR21_PORTL   (0x250+M32R_ICU_OFFSET)  /* MFT5 */
    190. 

  190. #define M32R_ICU_CR32_PORTL   (0x27C+M32R_ICU_OFFSET)  /* DMA0 */
    191. 

  191. #define M32R_ICU_CR33_PORTL   (0x280+M32R_ICU_OFFSET)  /* DMA1 */
    192. 

  192. #define M32R_ICU_CR48_PORTL   (0x2BC+M32R_ICU_OFFSET)  /* SIO0 */
    193. 

  193. #define M32R_ICU_CR49_PORTL   (0x2C0+M32R_ICU_OFFSET)  /* SIO0 */
    194. 

  194. #define M32R_ICU_CR50_PORTL   (0x2C4+M32R_ICU_OFFSET)  /* SIO1 */
    195. 

  195. #define M32R_ICU_CR51_PORTL   (0x2C8+M32R_ICU_OFFSET)  /* SIO1 */
    196. 

  196. #define M32R_ICU_CR52_PORTL   (0x2CC+M32R_ICU_OFFSET)  /* SIO2 */
    197. 

  197. #define M32R_ICU_CR53_PORTL   (0x2D0+M32R_ICU_OFFSET)  /* SIO2 */
    198. 

  198. #define M32R_ICU_CR54_PORTL   (0x2D4+M32R_ICU_OFFSET)  /* SIO3 */
    199. 

  199. #define M32R_ICU_CR55_PORTL   (0x2D8+M32R_ICU_OFFSET)  /* SIO3 */
    200. 

  200. #define M32R_ICU_CR56_PORTL   (0x2DC+M32R_ICU_OFFSET)  /* SIO4 */
    201. 

  201. #define M32R_ICU_CR57_PORTL   (0x2E0+M32R_ICU_OFFSET)  /* SIO4 */
    202. 

  202. 

  203. #ifdef CONFIG_SMP
    204. 

  204. #define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET)  /* IPI0 */
    205. 

  205. #define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET)  /* IPI1 */
    206. 

  206. #define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET)  /* IPI2 */
    207. 

  207. #define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET)  /* IPI3 */
    208. 

  208. #define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET)  /* IPI4 */
    209. 

  209. #define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET)  /* IPI5 */
    210.