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aiot
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waterDataPreprocessing
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dataProcessing
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levelDataPreprocessingThread.h

levelDataPreprocessingThread.h 18 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF538_H
    8. 

  8. #define _DEF_BF538_H
    9. 

  9. 

  10. /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
    11. 

  11. #define	PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
    12. 

  12. #define	PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
    13. 

  13. #define	VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
    14. 

  14. #define	PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
    15. 

  15. #define	PLL_LOCKCNT		0xFFC00010	/* PLL Lock	Count register (16-bit) */
    16. 

  16. #define	CHIPID			0xFFC00014	/* Chip	ID Register */
    17. 

  17. 

  18. /* CHIPID Masks */
    19. 

  19. #define CHIPID_VERSION         0xF0000000
    20. 

  20. #define CHIPID_FAMILY          0x0FFFF000
    21. 

  21. #define CHIPID_MANUFACTURE     0x00000FFE
    22. 

  22. 

  23. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
    24. 

  24. #define	SWRST			0xFFC00100  /* Software	Reset Register (16-bit) */
    25. 

  25. #define	SYSCR			0xFFC00104  /* System Configuration registe */
    26. 

  26. #define	SIC_RVECT		0xFFC00108
    27. 

  27. #define	SIC_IMASK0		0xFFC0010C  /* Interrupt Mask Register */
    28. 

  28. #define	SIC_IAR0		0xFFC00110  /* Interrupt Assignment Register 0 */
    29. 

  29. #define	SIC_IAR1		0xFFC00114  /* Interrupt Assignment Register 1 */
    30. 

  30. #define	SIC_IAR2		0xFFC00118  /* Interrupt Assignment Register 2 */
    31. 

  31. #define	SIC_IAR3			0xFFC0011C	/* Interrupt Assignment	Register 3 */
    32. 

  32. #define	SIC_ISR0			0xFFC00120  /* Interrupt Status	Register */
    33. 

  33. #define	SIC_IWR0			0xFFC00124  /* Interrupt Wakeup	Register */
    34. 

  34. #define	SIC_IMASK1			0xFFC00128	/* Interrupt Mask Register 1 */
    35. 

  35. #define	SIC_ISR1			0xFFC0012C	/* Interrupt Status Register 1 */
    36. 

  36. #define	SIC_IWR1			0xFFC00130	/* Interrupt Wakeup Register 1 */
    37. 

  37. #define	SIC_IAR4			0xFFC00134	/* Interrupt Assignment	Register 4 */
    38. 

  38. #define	SIC_IAR5			0xFFC00138	/* Interrupt Assignment	Register 5 */
    39. 

  39. #define	SIC_IAR6			0xFFC0013C	/* Interrupt Assignment	Register 6 */
    40. 

  40. 

  41. 

  42. /* Watchdog Timer (0xFFC00200 -	0xFFC002FF) */
    43. 

  43. #define	WDOG_CTL	0xFFC00200  /* Watchdog	Control	Register */
    44. 

  44. #define	WDOG_CNT	0xFFC00204  /* Watchdog	Count Register */
    45. 

  45. #define	WDOG_STAT	0xFFC00208  /* Watchdog	Status Register */
    46. 

  46. 

  47. 

  48. /* Real	Time Clock (0xFFC00300 - 0xFFC003FF) */
    49. 

  49. #define	RTC_STAT	0xFFC00300  /* RTC Status Register */
    50. 

  50. #define	RTC_ICTL	0xFFC00304  /* RTC Interrupt Control Register */
    51. 

  51. #define	RTC_ISTAT	0xFFC00308  /* RTC Interrupt Status Register */
    52. 

  52. #define	RTC_SWCNT	0xFFC0030C  /* RTC Stopwatch Count Register */
    53. 

  53. #define	RTC_ALARM	0xFFC00310  /* RTC Alarm Time Register */
    54. 

  54. #define	RTC_FAST	0xFFC00314  /* RTC Prescaler Enable Register */
    55. 

  55. #define	RTC_PREN		0xFFC00314  /* RTC Prescaler Enable Register (alternate	macro) */
    56. 

  56. 

  57. 

  58. /* UART0 Controller (0xFFC00400	- 0xFFC004FF) */
    59. 

  59. #define	UART0_THR	      0xFFC00400  /* Transmit Holding register */
    60. 

  60. #define	UART0_RBR	      0xFFC00400  /* Receive Buffer register */
    61. 

  61. #define	UART0_DLL	      0xFFC00400  /* Divisor Latch (Low-Byte) */
    62. 

  62. #define	UART0_IER	      0xFFC00404  /* Interrupt Enable Register */
    63. 

  63. #define	UART0_DLH	      0xFFC00404  /* Divisor Latch (High-Byte) */
    64. 

  64. #define	UART0_IIR	      0xFFC00408  /* Interrupt Identification Register */
    65. 

  65. #define	UART0_LCR	      0xFFC0040C  /* Line Control Register */
    66. 

  66. #define	UART0_MCR			 0xFFC00410  /*	Modem Control Register */
    67. 

  67. #define	UART0_LSR	      0xFFC00414  /* Line Status Register */
    68. 

  68. #define	UART0_SCR	      0xFFC0041C  /* SCR Scratch Register */
    69. 

  69. #define	UART0_GCTL		     0xFFC00424	 /* Global Control Register */
    70. 

  70. 

  71. 

  72. /* SPI0	Controller (0xFFC00500 - 0xFFC005FF) */
    73. 

  73. 

  74. #define	SPI0_CTL			0xFFC00500  /* SPI0 Control Register */
    75. 

  75. #define	SPI0_FLG			0xFFC00504  /* SPI0 Flag register */
    76. 

  76. #define	SPI0_STAT			0xFFC00508  /* SPI0 Status register */
    77. 

  77. #define	SPI0_TDBR			0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
    78. 

  78. #define	SPI0_RDBR			0xFFC00510  /* SPI0 Receive Data Buffer	Register */
    79. 

  79. #define	SPI0_BAUD			0xFFC00514  /* SPI0 Baud rate Register */
    80. 

  80. #define	SPI0_SHADOW			0xFFC00518  /* SPI0_RDBR Shadow	Register */
    81. 

  81. #define SPI0_REGBASE			SPI0_CTL
    82. 

  82. 

  83. 

  84. /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
    85. 

  85. #define	TIMER0_CONFIG			0xFFC00600     /* Timer	0 Configuration	Register */
    86. 

  86. #define	TIMER0_COUNTER				0xFFC00604     /* Timer	0 Counter Register */
    87. 

  87. #define	TIMER0_PERIOD			0xFFC00608     /* Timer	0 Period Register */
    88. 

  88. #define	TIMER0_WIDTH			0xFFC0060C     /* Timer	0 Width	Register */
    89. 

  89. 

  90. #define	TIMER1_CONFIG			0xFFC00610	/*  Timer 1 Configuration Register   */
    91. 

  91. #define	TIMER1_COUNTER			0xFFC00614	/*  Timer 1 Counter Register	     */
    92. 

  92. #define	TIMER1_PERIOD			0xFFC00618	/*  Timer 1 Period Register	     */
    93. 

  93. #define	TIMER1_WIDTH			0xFFC0061C	/*  Timer 1 Width Register	     */
    94. 

  94. 

  95. #define	TIMER2_CONFIG			0xFFC00620	/* Timer 2 Configuration Register   */
    96. 

  96. #define	TIMER2_COUNTER			0xFFC00624	/* Timer 2 Counter Register	    */
    97. 

  97. #define	TIMER2_PERIOD			0xFFC00628	/* Timer 2 Period Register	    */
    98. 

  98. #define	TIMER2_WIDTH			0xFFC0062C	/* Timer 2 Width Register	    */
    99. 

  99. 

  100. #define	TIMER_ENABLE				0xFFC00640	/* Timer Enable	Register */
    101. 

  101. #define	TIMER_DISABLE				0xFFC00644	/* Timer Disable Register */
    102. 

  102. #define	TIMER_STATUS				0xFFC00648	/* Timer Status	Register */
    103. 

  103. 

  104. 

  105. /* Programmable	Flags (0xFFC00700 - 0xFFC007FF) */
    106. 

  106. #define	FIO_FLAG_D				0xFFC00700  /* Flag Mask to directly specify state of pins */
    107. 

  107. #define	FIO_FLAG_C			0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
    108. 

  108. #define	FIO_FLAG_S			0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
    109. 

  109. #define	FIO_FLAG_T					0xFFC0070C  /* Flag Mask to directly toggle state of pins */
    110. 

  110. #define	FIO_MASKA_D			0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
    111. 

  111. #define	FIO_MASKA_C			0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
    112. 

  112. #define	FIO_MASKA_S			0xFFC00718  /* Flag Mask Interrupt A Register (set) */
    113. 

  113. #define	FIO_MASKA_T			0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
    114. 

  114. #define	FIO_MASKB_D			0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
    115. 

  115. #define	FIO_MASKB_C			0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
    116. 

  116. #define	FIO_MASKB_S			0xFFC00728  /* Flag Mask Interrupt B Register (set) */
    117. 

  117. #define	FIO_MASKB_T			0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
    118. 

  118. #define	FIO_DIR				0xFFC00730  /* Peripheral Flag Direction Register */
    119. 

  119. #define	FIO_POLAR			0xFFC00734  /* Flag Source Polarity Register */
    120. 

  120. #define	FIO_EDGE			0xFFC00738  /* Flag Source Sensitivity Register */
    121. 

  121. #define	FIO_BOTH			0xFFC0073C  /* Flag Set	on BOTH	Edges Register */
    122. 

  122. #define	FIO_INEN					0xFFC00740  /* Flag Input Enable Register  */
    123. 

  123. 

  124. 

  125. /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
    126. 

  126. #define	SPORT0_TCR1				0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
    127. 

  127. #define	SPORT0_TCR2				0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
    128. 

  128. #define	SPORT0_TCLKDIV			0xFFC00808  /* SPORT0 Transmit Clock Divider */
    129. 

  129. #define	SPORT0_TFSDIV			0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
    130. 

  130. #define	SPORT0_TX			0xFFC00810  /* SPORT0 TX Data Register */
    131. 

  131. #define	SPORT0_RX			0xFFC00818  /* SPORT0 RX Data Register */
    132. 

  132. #define	SPORT0_RCR1				0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
    133. 

  133. #define	SPORT0_RCR2				0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
    134. 

  134. #define	SPORT0_RCLKDIV			0xFFC00828  /* SPORT0 Receive Clock Divider */
    135. 

  135. #define	SPORT0_RFSDIV			0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
    136. 

  136. #define	SPORT0_STAT			0xFFC00830  /* SPORT0 Status Register */
    137. 

  137. #define	SPORT0_CHNL			0xFFC00834  /* SPORT0 Current Channel Register */
    138. 

  138. #define	SPORT0_MCMC1			0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
    139. 

  139. #define	SPORT0_MCMC2			0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
    140. 

  140. #define	SPORT0_MTCS0			0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
    141. 

  141. #define	SPORT0_MTCS1			0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
    142. 

  142. #define	SPORT0_MTCS2			0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
    143. 

  143. #define	SPORT0_MTCS3			0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
    144. 

  144. #define	SPORT0_MRCS0			0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
    145. 

  145. #define	SPORT0_MRCS1			0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
    146. 

  146. #define	SPORT0_MRCS2			0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
    147. 

  147. #define	SPORT0_MRCS3			0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
    148. 

  148. 

  149. 

  150. /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
    151. 

  151. #define	SPORT1_TCR1				0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
    152. 

  152. #define	SPORT1_TCR2				0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
    153. 

  153. #define	SPORT1_TCLKDIV			0xFFC00908  /* SPORT1 Transmit Clock Divider */
    154. 

  154. #define	SPORT1_TFSDIV			0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
    155. 

  155. #define	SPORT1_TX			0xFFC00910  /* SPORT1 TX Data Register */
    156. 

  156. #define	SPORT1_RX			0xFFC00918  /* SPORT1 RX Data Register */
    157. 

  157. #define	SPORT1_RCR1				0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
    158. 

  158. #define	SPORT1_RCR2				0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
    159. 

  159. #define	SPORT1_RCLKDIV			0xFFC00928  /* SPORT1 Receive Clock Divider */
    160. 

  160. #define	SPORT1_RFSDIV			0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
    161. 

  161. #define	SPORT1_STAT			0xFFC00930  /* SPORT1 Status Register */
    162. 

  162. #define	SPORT1_CHNL			0xFFC00934  /* SPORT1 Current Channel Register */
    163. 

  163. #define	SPORT1_MCMC1			0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
    164. 

  164. #define	SPORT1_MCMC2			0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
    165. 

  165. #define	SPORT1_MTCS0			0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
    166. 

  166. #define	SPORT1_MTCS1			0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
    167. 

  167. #define	SPORT1_MTCS2			0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
    168. 

  168. #define	SPORT1_MTCS3			0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
    169. 

  169. #define	SPORT1_MRCS0			0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
    170. 

  170. #define	SPORT1_MRCS1			0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
    171. 

  171. #define	SPORT1_MRCS2			0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
    172. 

  172. #define	SPORT1_MRCS3			0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
    173. 

  173. 

  174. 

  175. /* External Bus	Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
    176. 

  176. /* Asynchronous	Memory Controller  */
    177. 

  177. #define	EBIU_AMGCTL			0xFFC00A00  /* Asynchronous Memory Global Control Register */
    178. 

  178. #define	EBIU_AMBCTL0		0xFFC00A04  /* Asynchronous Memory Bank	Control	Register 0 */
    179. 

  179. #define	EBIU_AMBCTL1		0xFFC00A08  /* Asynchronous Memory Bank	Control	Register 1 */
    180. 

  180. 

  181. /* SDRAM Controller */
    182. 

  182. #define	EBIU_SDGCTL			0xFFC00A10  /* SDRAM Global Control Register */
    183. 

  183. #define	EBIU_SDBCTL			0xFFC00A14  /* SDRAM Bank Control Register */
    184. 

  184. #define	EBIU_SDRRC			0xFFC00A18  /* SDRAM Refresh Rate Control Register */
    185. 

  185. #define	EBIU_SDSTAT			0xFFC00A1C  /* SDRAM Status Register */
    186. 

  186. 

  187. 

  188. 

  189. /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
    190. 

  190. 

  191. #define	DMAC0_TC_PER			0xFFC00B0C	/* DMA Controller 0 Traffic Control Periods Register */
    192. 

  192. #define	DMAC0_TC_CNT			0xFFC00B10	/* DMA Controller 0 Traffic Control Current Counts Register */
    193. 

  193. 

  194. 

  195. 

  196. /* DMA Controller 0 (0xFFC00C00	- 0xFFC00FFF)							 */
    197. 

  197. 

  198. #define	DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
    199. 

  199. #define	DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register */
    200. 

  200. #define	DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register */
    201. 

  201. #define	DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register */
    202. 

  202. #define	DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register */
    203. 

  203. #define	DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register */
    204. 

  204. #define	DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
    205. 

  205. #define	DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
    206. 

  206. #define	DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register */
    207. 

  207. #define	DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
    208. 

  208. #define	DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map	Register */
    209. 

  209. #define	DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register */
    210. 

  210. #define	DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
    211. 

  211. 

  212. #define	DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
    213. 

  213. #define	DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register */
    214. 

  214. #define	DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register */
    215. 

  215. #define	DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register */
    216. 

  216. #define	DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register */
    217. 

  217. #define	DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register */
    218. 

  218. #define	DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
    219. 

  219. #define	DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
    220. 

  220. #define	DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register */
    221. 

  221. #define	DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
    222. 

  222. #define	DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map	Register */
    223. 

  223. #define	DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register */
    224. 

  224. #define	DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
    225. 

  225. 

  226. #define	DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
    227. 

  227. #define	DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register */
    228. 

  228. #define	DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register */
    229. 

  229. #define	DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register */
    230. 

  230. #define	DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register */
    231. 

  231. #define	DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register */
    232. 

  232. #define	DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
    233. 

  233. #define	DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
    234. 

  234. #define	DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register */
    235. 

  235. #define	DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
    236. 

  236. #define	DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map	Register */
    237. 

  237. #define	DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
    238. 

  238. #define	DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
    239. 

  239. 

  240. #define	DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
    241. 

  241. #define	DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register */
    242. 

  242. #define	DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register */
    243. 

  243. #define	DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register */
    244. 

  244. #define	DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register */
    245. 

  245. #define	DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register */
    246. 

  246. #define	DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
    247. 

  247. #define	DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
    248. 

  248. #define	DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register */
    249. 

  249. #define	DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
    250. 

  250. #define	DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map	Register */
    251. 

  251. #define	DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
    252. 

  252. #define	DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
    253. 

  253. 

  254. #define	DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
    255. 

  255. #define	DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register */
    256. 

  256. #define	DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register */
    257. 

  257. #define	DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register */
    258. 

  258. #define	DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register */
    259. 

  259. #define	DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register */
    260. 

  260. #define	DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
    261. 

  261. #define	DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
    262. 

  262. #define	DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register */
    263. 

  263. #define	DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
    264. 

  264. #define	DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map	Register */
    265. 

  265. #define	DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register */
    266. 

  266. #define	DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
    267. 

  267. 

  268. #define	DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
    269. 

  269. #define	DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register */
    270. 

  270. #define	DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register */
    271. 

  271. #define	DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register */
    272. 

  272. #define	DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register */
    273. 

  273. #define	DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register */
    274. 

  274. #define	DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
    275. 

  275. #define	DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
    276. 

  276. #define	DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register */
    277. 

  277. #define	DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
    278. 

  278. #define	DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map	Register */
    279. 

  279. #define	DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register */
    280. 

  280. #define	DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
    281. 

  281. 

  282. #define	DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
    283. 

  283. #define	DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register */
    284. 

  284. #define	DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register */
    285. 

  285. #define	DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register */
    286. 

  286. #define	DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register */
    287. 

  287. #define	DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register */
    288. 

  288. #define	DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
    289. 

  289. #define	DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
    290. 

  290. #define	DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register */
    291. 

  291. #define	DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
    292. 

  292. #define	DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map	Register */
    293. 

  293. #define	DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
    294.