waterPressureMemoryDefinition.h 11 KB

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  1. /*
  2. * arch/arm/mach-versatile/include/mach/platform.h
  3. *
  4. * Copyright (c) ARM Limited 2003. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #ifndef __address_h
  21. #define __address_h 1
  22. /*
  23. * Memory definitions
  24. */
  25. #define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
  26. #define VERSATILE_BOOT_ROM_HI 0x30000000
  27. #define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
  28. #define VERSATILE_BOOT_ROM_SIZE SZ_64M
  29. #define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
  30. #define VERSATILE_SSRAM_SIZE SZ_2M
  31. #define VERSATILE_FLASH_BASE 0x34000000
  32. #define VERSATILE_FLASH_SIZE SZ_64M
  33. /*
  34. * SDRAM
  35. */
  36. #define VERSATILE_SDRAM_BASE 0x00000000
  37. /*
  38. * Logic expansion modules
  39. *
  40. */
  41. /* ------------------------------------------------------------------------
  42. * Versatile Registers
  43. * ------------------------------------------------------------------------
  44. *
  45. */
  46. #define VERSATILE_SYS_ID_OFFSET 0x00
  47. #define VERSATILE_SYS_SW_OFFSET 0x04
  48. #define VERSATILE_SYS_LED_OFFSET 0x08
  49. #define VERSATILE_SYS_OSC0_OFFSET 0x0C
  50. #if defined(CONFIG_ARCH_VERSATILE_PB)
  51. #define VERSATILE_SYS_OSC1_OFFSET 0x10
  52. #define VERSATILE_SYS_OSC2_OFFSET 0x14
  53. #define VERSATILE_SYS_OSC3_OFFSET 0x18
  54. #define VERSATILE_SYS_OSC4_OFFSET 0x1C
  55. #elif defined(CONFIG_MACH_VERSATILE_AB)
  56. #define VERSATILE_SYS_OSC1_OFFSET 0x1C
  57. #endif
  58. #define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c
  59. #define VERSATILE_SYS_LOCK_OFFSET 0x20
  60. #define VERSATILE_SYS_100HZ_OFFSET 0x24
  61. #define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
  62. #define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
  63. #define VERSATILE_SYS_FLAGS_OFFSET 0x30
  64. #define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
  65. #define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
  66. #define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
  67. #define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
  68. #define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
  69. #define VERSATILE_SYS_RESETCTL_OFFSET 0x40
  70. #define VERSATILE_SYS_PCICTL_OFFSET 0x44
  71. #define VERSATILE_SYS_MCI_OFFSET 0x48
  72. #define VERSATILE_SYS_FLASH_OFFSET 0x4C
  73. #define VERSATILE_SYS_CLCD_OFFSET 0x50
  74. #define VERSATILE_SYS_CLCDSER_OFFSET 0x54
  75. #define VERSATILE_SYS_BOOTCS_OFFSET 0x58
  76. #define VERSATILE_SYS_24MHz_OFFSET 0x5C
  77. #define VERSATILE_SYS_MISC_OFFSET 0x60
  78. #define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
  79. #define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
  80. #define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
  81. #define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
  82. #define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
  83. #define VERSATILE_SYS_BASE 0x10000000
  84. #define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
  85. #define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
  86. #define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
  87. #define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
  88. #define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
  89. #if defined(CONFIG_ARCH_VERSATILE_PB)
  90. #define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
  91. #define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
  92. #define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
  93. #endif
  94. #define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
  95. #define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
  96. #define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
  97. #define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
  98. #define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
  99. #define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
  100. #define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
  101. #define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
  102. #define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
  103. #define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
  104. #define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
  105. #define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
  106. #define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
  107. #define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
  108. #define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
  109. #define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
  110. #define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
  111. #define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
  112. #define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
  113. #define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
  114. #define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
  115. #define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
  116. #define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
  117. #define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
  118. /*
  119. * Values for VERSATILE_SYS_RESET_CTRL
  120. */
  121. #define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
  122. #define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
  123. #define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
  124. #define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
  125. #define VERSATILE_SYS_CTRL_RESET_POR 0x05
  126. #define VERSATILE_SYS_CTRL_RESET_DoC 0x06
  127. #define VERSATILE_SYS_CTRL_LED (1 << 0)
  128. /* ------------------------------------------------------------------------
  129. * Versatile control registers
  130. * ------------------------------------------------------------------------
  131. */
  132. /*
  133. * VERSATILE_IDFIELD
  134. *
  135. * 31:24 = manufacturer (0x41 = ARM)
  136. * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
  137. * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
  138. * 11:4 = build value
  139. * 3:0 = revision number (0x1 = rev B (AHB))
  140. */
  141. /*
  142. * VERSATILE_SYS_LOCK
  143. * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
  144. * SYS_CLD, SYS_BOOTCS
  145. */
  146. #define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
  147. #define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
  148. /*
  149. * VERSATILE_SYS_FLASH
  150. */
  151. #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
  152. /*
  153. * VERSATILE_INTREG
  154. * - used to acknowledge and control MMCI and UART interrupts
  155. */
  156. #define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
  157. #define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
  158. #define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
  159. /* write 1 to acknowledge and clear */
  160. #define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
  161. #define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
  162. /*
  163. * VERSATILE peripheral addresses
  164. */
  165. #define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
  166. #define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
  167. #define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
  168. #define VERSATILE_AACI_BASE 0x10004000 /* Audio */
  169. #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
  170. #define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
  171. #define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
  172. #define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
  173. #define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
  174. #define VERSATILE_SCI1_BASE 0x1000A000
  175. #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
  176. /* 0x1000C000 - 0x1000CFFF = reserved */
  177. #define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
  178. #define VERSATILE_USB_BASE 0x10020000 /* USB */
  179. /* 0x10030000 - 0x100FFFFF = reserved */
  180. #define VERSATILE_SMC_BASE 0x10100000 /* SMC */
  181. #define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
  182. #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
  183. #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
  184. #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
  185. #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
  186. /* 0x10000000 - 0x100FFFFF */
  187. #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
  188. #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
  189. #define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
  190. #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
  191. #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
  192. #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
  193. #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
  194. #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
  195. #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
  196. #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */