aiot/waterHeterogeneousDataSynchronization/monitoringDataProcessing/preliminaryDataProcessing.h

/*
 * Copyright 2005-2010 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H

/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */

/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
#define bfin_read_CHIPID()                   bfin_read32(CHIPID)

/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define bfin_read_SWRST()                    bfin_read16(SWRST)
#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
#define bfin_read_SIC_RVECT()                bfin_read16(SIC_RVECT)
#define bfin_write_SIC_RVECT(val)            bfin_write16(SIC_RVECT,val)
#define bfin_read_SIC_IMASK0()               bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val)           bfin_write32(SIC_IMASK0,val)
#define bfin_read_SIC_IMASK1()               bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val)           bfin_write32(SIC_IMASK1,val)
#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
#define bfin_read_SIC_IAR4()                 bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val)             bfin_write32(SIC_IAR4,val)
#define bfin_read_SIC_IAR5()                 bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val)             bfin_write32(SIC_IAR5,val)
#define bfin_read_SIC_IAR6()                 bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val)             bfin_write32(SIC_IAR6,val)
#define bfin_read_SIC_IAR7()                 bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val)             bfin_write32(SIC_IAR7,val)
#define bfin_read_SIC_ISR0()                 bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val)             bfin_write32(SIC_ISR0,val)
#define bfin_read_SIC_ISR1()                 bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val)             bfin_write32(SIC_ISR1,val)
#define bfin_read_SIC_IWR0()                 bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val)             bfin_write32(SIC_IWR0,val)
#define bfin_read_SIC_IWR1()                 bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val)             bfin_write32(SIC_IWR1,val)

/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
#define bfin_read_SICB_SWRST()               bfin_read16(SICB_SWRST)
#define bfin_write_SICB_SWRST(val)           bfin_write16(SICB_SWRST,val)
#define bfin_read_SICB_SYSCR()               bfin_read16(SICB_SYSCR)
#define bfin_write_SICB_SYSCR(val)           bfin_write16(SICB_SYSCR,val)
#define bfin_read_SICB_RVECT()               bfin_read16(SICB_RVECT)
#define bfin_write_SICB_RVECT(val)           bfin_write16(SICB_RVECT,val)
#define bfin_read_SICB_IMASK0()              bfin_read32(SICB_IMASK0)
#define bfin_write_SICB_IMASK0(val)          bfin_write32(SICB_IMASK0,val)
#define bfin_read_SICB_IMASK1()              bfin_read32(SICB_IMASK1)
#define bfin_write_SICB_IMASK1(val)          bfin_write32(SICB_IMASK1,val)
#define bfin_read_SICB_IAR0()                bfin_read32(SICB_IAR0)
#define bfin_write_SICB_IAR0(val)            bfin_write32(SICB_IAR0,val)
#define bfin_read_SICB_IAR1()                bfin_read32(SICB_IAR1)
#define bfin_write_SICB_IAR1(val)            bfin_write32(SICB_IAR1,val)
#define bfin_read_SICB_IAR2()                bfin_read32(SICB_IAR2)
#define bfin_write_SICB_IAR2(val)            bfin_write32(SICB_IAR2,val)
#define bfin_read_SICB_IAR3()                bfin_read32(SICB_IAR3)
#define bfin_write_SICB_IAR3(val)            bfin_write32(SICB_IAR3,val)
#define bfin_read_SICB_IAR4()                bfin_read32(SICB_IAR4)
#define bfin_write_SICB_IAR4(val)            bfin_write32(SICB_IAR4,val)
#define bfin_read_SICB_IAR5()                bfin_read32(SICB_IAR5)
#define bfin_write_SICB_IAR5(val)            bfin_write32(SICB_IAR5,val)
#define bfin_read_SICB_IAR6()                bfin_read32(SICB_IAR6)
#define bfin_write_SICB_IAR6(val)            bfin_write32(SICB_IAR6,val)
#define bfin_read_SICB_IAR7()                bfin_read32(SICB_IAR7)
#define bfin_write_SICB_IAR7(val)            bfin_write32(SICB_IAR7,val)
#define bfin_read_SICB_ISR0()                bfin_read32(SICB_ISR0)
#define bfin_write_SICB_ISR0(val)            bfin_write32(SICB_ISR0,val)
#define bfin_read_SICB_ISR1()                bfin_read32(SICB_ISR1)
#define bfin_write_SICB_ISR1(val)            bfin_write32(SICB_ISR1,val)
#define bfin_read_SICB_IWR0()                bfin_read32(SICB_IWR0)
#define bfin_write_SICB_IWR0(val)            bfin_write32(SICB_IWR0,val)
#define bfin_read_SICB_IWR1()                bfin_read32(SICB_IWR1)
#define bfin_write_SICB_IWR1(val)            bfin_write32(SICB_IWR1,val)
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define bfin_read_WDOGA_CTL()                bfin_read16(WDOGA_CTL)
#define bfin_write_WDOGA_CTL(val)            bfin_write16(WDOGA_CTL,val)
#define bfin_read_WDOGA_CNT()                bfin_read32(WDOGA_CNT)
#define bfin_write_WDOGA_CNT(val)            bfin_write32(WDOGA_CNT,val)
#define bfin_read_WDOGA_STAT()               bfin_read32(WDOGA_STAT)
#define bfin_write_WDOGA_STAT(val)           bfin_write32(WDOGA_STAT,val)

/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
#define bfin_read_WDOGB_CTL()                bfin_read16(WDOGB_CTL)
#define bfin_write_WDOGB_CTL(val)            bfin_write16(WDOGB_CTL,val)
#define bfin_read_WDOGB_CNT()                bfin_read32(WDOGB_CNT)
#define bfin_write_WDOGB_CNT(val)            bfin_write32(WDOGB_CNT,val)
#define bfin_read_WDOGB_STAT()               bfin_read32(WDOGB_STAT)
#define bfin_write_WDOGB_STAT(val)           bfin_write32(WDOGB_STAT,val)

/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
#define bfin_read_UART_MSR()                 bfin_read16(UART_MSR)
#define bfin_write_UART_MSR(val)             bfin_write16(UART_MSR,val)
#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)

/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)

/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)