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aiot
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efDataStatistics
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dataSharedMemory
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memoryOperation.h

memoryOperation.h 5.3 KB
文件歷史 原始文件

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  1. /* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
    2. 

  2.  *
    3. 

  3.  * This software is licensed under the terms of the GNU General Public
    4. 

  4.  * License version 2, as published by the Free Software Foundation, and
    5. 

  5.  * may be copied, distributed, and modified under those terms.
    6. 

  6.  *
    7. 

  7.  * This program is distributed in the hope that it will be useful,
    8. 

  8.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    9. 

  9.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    10. 

  10.  * GNU General Public License for more details.
    11. 

  11.  *
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef __ASM_ARCH_MSM_IRQS_8X60_H
    15. 

  15. #define __ASM_ARCH_MSM_IRQS_8X60_H
    16. 

  16. 

  17. /* MSM ACPU Interrupt Numbers */
    18. 

  18. 

  19. /* 0-15:  STI/SGI (software triggered/generated interrupts)
    20. 

  20.  * 16-31: PPI (private peripheral interrupts)
    21. 

  21.  * 32+:   SPI (shared peripheral interrupts)
    22. 

  22.  */
    23. 

  23. 

  24. #define GIC_PPI_START 16
    25. 

  25. #define GIC_SPI_START 32
    26. 

  26. 

  27. #define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 0)
    28. 

  28. #define INT_GP_TIMER_EXP			(GIC_PPI_START + 1)
    29. 

  29. #define INT_GP_TIMER2_EXP			(GIC_PPI_START + 2)
    30. 

  30. #define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 3)
    31. 

  31. #define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
    32. 

  32. #define AVS_SVICINT				(GIC_PPI_START + 5)
    33. 

  33. #define AVS_SVICINTSWDONE			(GIC_PPI_START + 6)
    34. 

  34. #define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 7)
    35. 

  35. #define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 8)
    36. 

  36. #define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 9)
    37. 

  37. #define SC_AVSCPUXDOWN				(GIC_PPI_START + 10)
    38. 

  38. #define SC_AVSCPUXUP				(GIC_PPI_START + 11)
    39. 

  39. #define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 12)
    40. 

  40. /* PPI 13 to 15 are unused */
    41. 

  41. 

  42. 

  43. #define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
    44. 

  44. #define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
    45. 

  45. #define SC_SICL2ACGIRPTREQ			(GIC_SPI_START + 2)
    46. 

  46. #define NC					(GIC_SPI_START + 3)
    47. 

  47. #define TLMM_SCSS_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
    48. 

  48. #define TLMM_SCSS_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
    49. 

  49. #define TLMM_SCSS_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
    50. 

  50. #define TLMM_SCSS_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
    51. 

  51. #define TLMM_SCSS_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
    52. 

  52. #define TLMM_SCSS_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
    53. 

  53. #define TLMM_SCSS_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
    54. 

  54. #define TLMM_SCSS_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
    55. 

  55. #define TLMM_SCSS_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
    56. 

  56. #define TLMM_SCSS_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
    57. 

  57. #define PM8058_SEC_IRQ_N			(GIC_SPI_START + 14)
    58. 

  58. #define PM8901_SEC_IRQ_N			(GIC_SPI_START + 15)
    59. 

  59. #define TLMM_SCSS_SUMMARY_IRQ			(GIC_SPI_START + 16)
    60. 

  60. #define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
    61. 

  61. #define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
    62. 

  62. #define RPM_SCSS_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
    63. 

  63. #define RPM_SCSS_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
    64. 

  64. #define RPM_SCSS_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
    65. 

  65. #define RPM_SCSS_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
    66. 

  66. #define RPM_SCSS_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
    67. 

  67. #define RPM_SCSS_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
    68. 

  68. #define RPM_SCSS_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
    69. 

  69. #define RPM_SCSS_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
    70. 

  70. #define SSBI2_2_SC_CPU0_SECURE_INT		(GIC_SPI_START + 27)
    71. 

  71. #define SSBI2_2_SC_CPU0_NON_SECURE_INT		(GIC_SPI_START + 28)
    72. 

  72. #define SSBI2_1_SC_CPU0_SECURE_INT		(GIC_SPI_START + 29)
    73. 

  73. #define SSBI2_1_SC_CPU0_NON_SECURE_INT		(GIC_SPI_START + 30)
    74. 

  74. #define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
    75. 

  75. #define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
    76. 

  76. #define MARM_FIQ				(GIC_SPI_START + 33)
    77. 

  77. #define MARM_IRQ				(GIC_SPI_START + 34)
    78. 

  78. #define MARM_L2CC_IRQ				(GIC_SPI_START + 35)
    79. 

  79. #define MARM_WDOG_EXPIRED			(GIC_SPI_START + 36)
    80. 

  80. #define MARM_SCSS_GP_IRQ_0			(GIC_SPI_START + 37)
    81. 

  81. #define MARM_SCSS_GP_IRQ_1			(GIC_SPI_START + 38)
    82. 

  82. #define MARM_SCSS_GP_IRQ_2			(GIC_SPI_START + 39)
    83. 

  83. #define MARM_SCSS_GP_IRQ_3			(GIC_SPI_START + 40)
    84. 

  84. #define MARM_SCSS_GP_IRQ_4			(GIC_SPI_START + 41)
    85. 

  85. #define MARM_SCSS_GP_IRQ_5			(GIC_SPI_START + 42)
    86. 

  86. #define MARM_SCSS_GP_IRQ_6			(GIC_SPI_START + 43)
    87. 

  87. #define MARM_SCSS_GP_IRQ_7			(GIC_SPI_START + 44)
    88. 

  88. #define MARM_SCSS_GP_IRQ_8			(GIC_SPI_START + 45)
    89. 

  89. #define MARM_SCSS_GP_IRQ_9			(GIC_SPI_START + 46)
    90. 

  90. #define VPE_IRQ					(GIC_SPI_START + 47)
    91. 

  91. #define VFE_IRQ					(GIC_SPI_START + 48)
    92. 

  92. #define VCODEC_IRQ				(GIC_SPI_START + 49)
    93. 

  93. #define TV_ENC_IRQ				(GIC_SPI_START + 50)
    94. 

  94. #define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
    95. 

  95. #define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
    96. 

  96. #define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
    97. 

  97. #define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
    98. 

  98. #define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
    99. 

  99. #define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
    100. 

  100. #define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
    101. 

  101. #define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
    102. 

  102. #define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
    103. 

  103. #define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
    104. 

  104. #define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
    105. 

  105. #define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
    106. 

  106. #define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
    107. 

  107. #define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
    108. 

  108. #define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
    109. 

  109. #define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
    110. 

  110. #define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
    111. 

  111. #define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
    112. 

  112. #define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
    113. 

  113. #define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
    114. 

  114. #define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
    115. 

  115. #define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
    116. 

  116. #define ROT_IRQ					(GIC_SPI_START + 73)
    117.