| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123 | /* * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */#ifndef _CDEF_BF538_H#define _CDEF_BF538_H#define bfin_writePTR(addr, val) bfin_write32(addr, val)#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)#define bfin_read_CHIPID()             bfin_read32(CHIPID)#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)#define bfin_read_SWRST()              bfin_read16(SWRST)#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)#define bfin_read_SYSCR()              bfin_read16(SYSCR)#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)#define bfin_read_SIC_RVECT()          bfin_readPTR(SIC_RVECT)#define bfin_write_SIC_RVECT(val)      bfin_writePTR(SIC_RVECT, val)#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)#define bfin_read_SIC_IMASK(x)	       bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))#define bfin_write_SIC_IMASK(x, val)   bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)#define bfin_read_SIC_ISR(x)           bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))#define bfin_write_SIC_ISR(x, val)     bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)#define bfin_read_SIC_IWR(x)           bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))#define bfin_write_SIC_IWR(x, val)     bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
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