| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475 | /* * linux/arch/arm/mach-sa1100/jornada720.c * * HP Jornada720 init code * * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl> *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */#include <linux/init.h>#include <linux/kernel.h>#include <linux/tty.h>#include <linux/delay.h>#include <linux/platform_data/sa11x0-serial.h>#include <linux/platform_device.h>#include <linux/ioport.h>#include <linux/mtd/mtd.h>#include <linux/mtd/partitions.h>#include <video/s1d13xxxfb.h>#include <asm/hardware/sa1111.h>#include <asm/page.h>#include <asm/mach-types.h>#include <asm/setup.h>#include <asm/mach/arch.h>#include <asm/mach/flash.h>#include <asm/mach/map.h>#include <mach/hardware.h>#include <mach/irqs.h>#include "generic.h"/* * HP Documentation referred in this file: * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt *//* line 110 of HP's doc */#define TUCR_VAL	0x20000400/* memory space (line 52 of HP's doc) */#define SA1111REGSTART	0x40000000#define SA1111REGLEN	0x00002000#define EPSONREGSTART	0x48000000#define EPSONREGLEN	0x00100000#define EPSONFBSTART	0x48200000/* 512kB framebuffer */#define EPSONFBLEN	512*1024static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {	/* line 344 of HP's doc */	{0x0001,0x00},	// Miscellaneous Register	{0x01FC,0x00},	// Display Mode Register	{0x0004,0x00},	// General IO Pins Configuration Register 0	{0x0005,0x00},	// General IO Pins Configuration Register 1	{0x0008,0x00},	// General IO Pins Control Register 0	{0x0009,0x00},	// General IO Pins Control Register 1	{0x0010,0x01},	// Memory Clock Configuration Register	{0x0014,0x11},	// LCD Pixel Clock Configuration Register	{0x0018,0x01},	// CRT/TV Pixel Clock Configuration Register	{0x001C,0x01},	// MediaPlug Clock Configuration Register	{0x001E,0x01},	// CPU To Memory Wait State Select Register	{0x0020,0x00},	// Memory Configuration Register	{0x0021,0x45},	// DRAM Refresh Rate Register	{0x002A,0x01},	// DRAM Timings Control Register 0	{0x002B,0x03},	// DRAM Timings Control Register 1	{0x0030,0x1c},	// Panel Type Register	{0x0031,0x00},	// MOD Rate Register
 |