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hiddenDangerAnalysis.h

hiddenDangerAnalysis.h 4.4 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2010 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the Clear BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _CDEF_BF512_H
    8. 

  8. #define _CDEF_BF512_H
    9. 

  9. 

  10. /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
    11. 

  11. #define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)
    12. 

  12. #define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)
    13. 

  13. #define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)
    14. 

  14. #define bfin_read_VR_CTL()			bfin_read16(VR_CTL)
    15. 

  15. #define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)
    16. 

  16. #define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)
    17. 

  17. #define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
    18. 

  18. #define bfin_write_PLL_LOCKCNT(val)		bfin_write16(PLL_LOCKCNT, val)
    19. 

  19. #define bfin_read_CHIPID()			bfin_read32(CHIPID)
    20. 

  20. #define bfin_write_CHIPID(val)			bfin_write32(CHIPID, val)
    21. 

  21. 

  22. 

  23. /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
    24. 

  24. #define bfin_read_SWRST()			bfin_read16(SWRST)
    25. 

  25. #define bfin_write_SWRST(val)			bfin_write16(SWRST, val)
    26. 

  26. #define bfin_read_SYSCR()			bfin_read16(SYSCR)
    27. 

  27. #define bfin_write_SYSCR(val)			bfin_write16(SYSCR, val)
    28. 

  28. 

  29. #define bfin_read_SIC_RVECT()			bfin_read32(SIC_RVECT)
    30. 

  30. #define bfin_write_SIC_RVECT(val)		bfin_write32(SIC_RVECT, val)
    31. 

  31. #define bfin_read_SIC_IMASK0()			bfin_read32(SIC_IMASK0)
    32. 

  32. #define bfin_write_SIC_IMASK0(val)		bfin_write32(SIC_IMASK0, val)
    33. 

  33. #define bfin_read_SIC_IMASK(x)			bfin_read32(SIC_IMASK0 + (x << 6))
    34. 

  34. #define bfin_write_SIC_IMASK(x, val)		bfin_write32((SIC_IMASK0 + (x << 6)), val)
    35. 

  35. 

  36. #define bfin_read_SIC_IAR0()			bfin_read32(SIC_IAR0)
    37. 

  37. #define bfin_write_SIC_IAR0(val)		bfin_write32(SIC_IAR0, val)
    38. 

  38. #define bfin_read_SIC_IAR1()			bfin_read32(SIC_IAR1)
    39. 

  39. #define bfin_write_SIC_IAR1(val)		bfin_write32(SIC_IAR1, val)
    40. 

  40. #define bfin_read_SIC_IAR2()			bfin_read32(SIC_IAR2)
    41. 

  41. #define bfin_write_SIC_IAR2(val)		bfin_write32(SIC_IAR2, val)
    42. 

  42. #define bfin_read_SIC_IAR3()			bfin_read32(SIC_IAR3)
    43. 

  43. #define bfin_write_SIC_IAR3(val)		bfin_write32(SIC_IAR3, val)
    44. 

  44. 

  45. #define bfin_read_SIC_ISR0()			bfin_read32(SIC_ISR0)
    46. 

  46. #define bfin_write_SIC_ISR0(val)		bfin_write32(SIC_ISR0, val)
    47. 

  47. #define bfin_read_SIC_ISR(x)			bfin_read32(SIC_ISR0 + (x << 6))
    48. 

  48. #define bfin_write_SIC_ISR(x, val)		bfin_write32((SIC_ISR0 + (x << 6)), val)
    49. 

  49. 

  50. #define bfin_read_SIC_IWR0()			bfin_read32(SIC_IWR0)
    51. 

  51. #define bfin_write_SIC_IWR0(val)		bfin_write32(SIC_IWR0, val)
    52. 

  52. #define bfin_read_SIC_IWR(x)			bfin_read32(SIC_IWR0 + (x << 6))
    53. 

  53. #define bfin_write_SIC_IWR(x, val)		bfin_write32((SIC_IWR0 + (x << 6)), val)
    54. 

  54. 

  55. /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
    56. 

  56. 

  57. #define bfin_read_SIC_IMASK1()			bfin_read32(SIC_IMASK1)
    58. 

  58. #define bfin_write_SIC_IMASK1(val)		bfin_write32(SIC_IMASK1, val)
    59. 

  59. #define bfin_read_SIC_IAR4()			bfin_read32(SIC_IAR4)
    60. 

  60. #define bfin_write_SIC_IAR4(val)		bfin_write32(SIC_IAR4, val)
    61. 

  61. #define bfin_read_SIC_IAR5()			bfin_read32(SIC_IAR5)
    62. 

  62. #define bfin_write_SIC_IAR5(val)		bfin_write32(SIC_IAR5, val)
    63. 

  63. #define bfin_read_SIC_IAR6()			bfin_read32(SIC_IAR6)
    64. 

  64. #define bfin_write_SIC_IAR6(val)		bfin_write32(SIC_IAR6, val)
    65. 

  65. #define bfin_read_SIC_IAR7()			bfin_read32(SIC_IAR7)
    66. 

  66. #define bfin_write_SIC_IAR7(val)		bfin_write32(SIC_IAR7, val)
    67. 

  67. #define bfin_read_SIC_ISR1()			bfin_read32(SIC_ISR1)
    68. 

  68. #define bfin_write_SIC_ISR1(val)		bfin_write32(SIC_ISR1, val)
    69. 

  69. #define bfin_read_SIC_IWR1()			bfin_read32(SIC_IWR1)
    70. 

  70. #define bfin_write_SIC_IWR1(val)		bfin_write32(SIC_IWR1, val)
    71. 

  71. 

  72. /* Watchdog Timer		(0xFFC00200 - 0xFFC002FF)									*/
    73. 

  73. #define bfin_read_WDOG_CTL()			bfin_read16(WDOG_CTL)
    74. 

  74. #define bfin_write_WDOG_CTL(val)		bfin_write16(WDOG_CTL, val)
    75. 

  75. #define bfin_read_WDOG_CNT()			bfin_read32(WDOG_CNT)
    76. 

  76. #define bfin_write_WDOG_CNT(val)		bfin_write32(WDOG_CNT, val)
    77. 

  77. #define bfin_read_WDOG_STAT()			bfin_read32(WDOG_STAT)
    78. 

  78. #define bfin_write_WDOG_STAT(val)		bfin_write32(WDOG_STAT, val)
    79. 

  79. 

  80. 

  81. /* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
    82. 

  82. #define bfin_read_RTC_STAT()			bfin_read32(RTC_STAT)
    83. 

  83. #define bfin_write_RTC_STAT(val)		bfin_write32(RTC_STAT, val)
    84. 

  84. #define bfin_read_RTC_ICTL()			bfin_read16(RTC_ICTL)
    85. 

  85. #define bfin_write_RTC_ICTL(val)		bfin_write16(RTC_ICTL, val)
    86. 

  86. #define bfin_read_RTC_ISTAT()			bfin_read16(RTC_ISTAT)
    87. 

  87. #define bfin_write_RTC_ISTAT(val)		bfin_write16(RTC_ISTAT, val)
    88. 

  88. #define bfin_read_RTC_SWCNT()			bfin_read16(RTC_SWCNT)
    89. 

  89. #define bfin_write_RTC_SWCNT(val)		bfin_write16(RTC_SWCNT, val)
    90. 

  90. #define bfin_read_RTC_ALARM()			bfin_read32(RTC_ALARM)
    91. 

  91. #define bfin_write_RTC_ALARM(val)		bfin_write32(RTC_ALARM, val)
    92. 

  92. #define bfin_read_RTC_FAST()			bfin_read16(RTC_FAST)
    93. 

  93. #define bfin_write_RTC_FAST(val)		bfin_write16(RTC_FAST, val)
    94.