aiot/waterInvestigationHiddenDanger/analysisOfLeakageHiddenDanger/synchronousMemoryDatabase.c

/*
 * sh7372 processor support - PFC hardware block
 *
 * Copyright (C) 2010  Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on
 * sh7367 processor support - PFC hardware block
 * Copyright (C) 2010  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sh_pfc.h>
#include <mach/irqs.h>
#include <mach/sh7372.h>

#define CPU_ALL_PORT(fn, pfx, sfx) \
	PORT_10(fn, pfx, sfx),		PORT_90(fn, pfx, sfx), \
	PORT_10(fn, pfx##10, sfx),	PORT_10(fn, pfx##11, sfx), \
	PORT_10(fn, pfx##12, sfx),	PORT_10(fn, pfx##13, sfx), \
	PORT_10(fn, pfx##14, sfx),	PORT_10(fn, pfx##15, sfx), \
	PORT_10(fn, pfx##16, sfx),	PORT_10(fn, pfx##17, sfx), \
	PORT_10(fn, pfx##18, sfx),	PORT_1(fn, pfx##190, sfx)

enum {
	PINMUX_RESERVED = 0,

	/* PORT0_DATA -> PORT190_DATA */
	PINMUX_DATA_BEGIN,
	PORT_ALL(DATA),
	PINMUX_DATA_END,

	/* PORT0_IN -> PORT190_IN */
	PINMUX_INPUT_BEGIN,
	PORT_ALL(IN),
	PINMUX_INPUT_END,

	/* PORT0_IN_PU -> PORT190_IN_PU */
	PINMUX_INPUT_PULLUP_BEGIN,
	PORT_ALL(IN_PU),
	PINMUX_INPUT_PULLUP_END,

	/* PORT0_IN_PD -> PORT190_IN_PD */
	PINMUX_INPUT_PULLDOWN_BEGIN,
	PORT_ALL(IN_PD),
	PINMUX_INPUT_PULLDOWN_END,

	/* PORT0_OUT -> PORT190_OUT */
	PINMUX_OUTPUT_BEGIN,
	PORT_ALL(OUT),
	PINMUX_OUTPUT_END,

	PINMUX_FUNCTION_BEGIN,
	PORT_ALL(FN_IN),	/* PORT0_FN_IN	-> PORT190_FN_IN */
	PORT_ALL(FN_OUT),	/* PORT0_FN_OUT	-> PORT190_FN_OUT */
	PORT_ALL(FN0),		/* PORT0_FN0	-> PORT190_FN0 */
	PORT_ALL(FN1),		/* PORT0_FN1	-> PORT190_FN1 */
	PORT_ALL(FN2),		/* PORT0_FN2	-> PORT190_FN2 */
	PORT_ALL(FN3),		/* PORT0_FN3	-> PORT190_FN3 */
	PORT_ALL(FN4),		/* PORT0_FN4	-> PORT190_FN4 */
	PORT_ALL(FN5),		/* PORT0_FN5	-> PORT190_FN5 */
	PORT_ALL(FN6),		/* PORT0_FN6	-> PORT190_FN6 */
	PORT_ALL(FN7),		/* PORT0_FN7	-> PORT190_FN7 */

	MSEL1CR_31_0,	MSEL1CR_31_1,
	MSEL1CR_30_0,	MSEL1CR_30_1,
	MSEL1CR_29_0,	MSEL1CR_29_1,
	MSEL1CR_28_0,	MSEL1CR_28_1,
	MSEL1CR_27_0,	MSEL1CR_27_1,
	MSEL1CR_26_0,	MSEL1CR_26_1,
	MSEL1CR_16_0,	MSEL1CR_16_1,
	MSEL1CR_15_0,	MSEL1CR_15_1,
	MSEL1CR_14_0,	MSEL1CR_14_1,
	MSEL1CR_13_0,	MSEL1CR_13_1,
	MSEL1CR_12_0,	MSEL1CR_12_1,
	MSEL1CR_9_0,	MSEL1CR_9_1,
	MSEL1CR_8_0,	MSEL1CR_8_1,
	MSEL1CR_7_0,	MSEL1CR_7_1,
	MSEL1CR_6_0,	MSEL1CR_6_1,
	MSEL1CR_4_0,	MSEL1CR_4_1,
	MSEL1CR_3_0,	MSEL1CR_3_1,
	MSEL1CR_2_0,	MSEL1CR_2_1,
	MSEL1CR_0_0,	MSEL1CR_0_1,

	MSEL3CR_27_0,	MSEL3CR_27_1,
	MSEL3CR_26_0,	MSEL3CR_26_1,
	MSEL3CR_21_0,	MSEL3CR_21_1,
	MSEL3CR_20_0,	MSEL3CR_20_1,
	MSEL3CR_15_0,	MSEL3CR_15_1,
	MSEL3CR_9_0,	MSEL3CR_9_1,
	MSEL3CR_6_0,	MSEL3CR_6_1,

	MSEL4CR_19_0,	MSEL4CR_19_1,
	MSEL4CR_18_0,	MSEL4CR_18_1,
	MSEL4CR_17_0,	MSEL4CR_17_1,
	MSEL4CR_16_0,	MSEL4CR_16_1,
	MSEL4CR_15_0,	MSEL4CR_15_1,
	MSEL4CR_14_0,	MSEL4CR_14_1,
	MSEL4CR_10_0,	MSEL4CR_10_1,
	MSEL4CR_6_0,	MSEL4CR_6_1,
	MSEL4CR_4_0,	MSEL4CR_4_1,
	MSEL4CR_1_0,	MSEL4CR_1_1,
	PINMUX_FUNCTION_END,

	PINMUX_MARK_BEGIN,

	/* IRQ */
	IRQ0_6_MARK,	IRQ0_162_MARK,	IRQ1_MARK,	IRQ2_4_MARK,
	IRQ2_5_MARK,	IRQ3_8_MARK,	IRQ3_16_MARK,	IRQ4_17_MARK,
	IRQ4_163_MARK,	IRQ5_MARK,	IRQ6_39_MARK,	IRQ6_164_MARK,
	IRQ7_40_MARK,	IRQ7_167_MARK,	IRQ8_41_MARK,	IRQ8_168_MARK,
	IRQ9_42_MARK,	IRQ9_169_MARK,	IRQ10_MARK,	IRQ11_MARK,
	IRQ12_80_MARK,	IRQ12_137_MARK,	IRQ13_81_MARK,	IRQ13_145_MARK,
	IRQ14_82_MARK,	IRQ14_146_MARK,	IRQ15_83_MARK,	IRQ15_147_MARK,
	IRQ16_84_MARK,	IRQ16_170_MARK,	IRQ17_MARK,	IRQ18_MARK,
	IRQ19_MARK,	IRQ20_MARK,	IRQ21_MARK,	IRQ22_MARK,
	IRQ23_MARK,	IRQ24_MARK,	IRQ25_MARK,	IRQ26_121_MARK,
	IRQ26_172_MARK,	IRQ27_122_MARK,	IRQ27_180_MARK,	IRQ28_123_MARK,
	IRQ28_181_MARK,	IRQ29_129_MARK,	IRQ29_182_MARK,	IRQ30_130_MARK,
	IRQ30_183_MARK,	IRQ31_138_MARK,	IRQ31_184_MARK,

	/* MSIOF0 */
	MSIOF0_TSYNC_MARK,	MSIOF0_TSCK_MARK,	MSIOF0_RXD_MARK,
	MSIOF0_RSCK_MARK,	MSIOF0_RSYNC_MARK,	MSIOF0_MCK0_MARK,
	MSIOF0_MCK1_MARK,	MSIOF0_SS1_MARK,	MSIOF0_SS2_MARK,
	MSIOF0_TXD_MARK,

	/* MSIOF1 */
	MSIOF1_TSCK_39_MARK,	MSIOF1_TSYNC_40_MARK,
	MSIOF1_TSCK_88_MARK,	MSIOF1_TSYNC_89_MARK,
	MSIOF1_TXD_41_MARK,	MSIOF1_RXD_42_MARK,
	MSIOF1_TXD_90_MARK,	MSIOF1_RXD_91_MARK,
	MSIOF1_SS1_43_MARK,	MSIOF1_SS2_44_MARK,
	MSIOF1_SS1_92_MARK,	MSIOF1_SS2_93_MARK,
	MSIOF1_RSCK_MARK,	MSIOF1_RSYNC_MARK,
	MSIOF1_MCK0_MARK,	MSIOF1_MCK1_MARK,

	/* MSIOF2 */
	MSIOF2_RSCK_MARK,	MSIOF2_RSYNC_MARK,	MSIOF2_MCK0_MARK,
	MSIOF2_MCK1_MARK,	MSIOF2_SS1_MARK,	MSIOF2_SS2_MARK,
	MSIOF2_TSYNC_MARK,	MSIOF2_TSCK_MARK,	MSIOF2_RXD_MARK,
	MSIOF2_TXD_MARK,

	/* BBIF1 */
	BBIF1_RXD_MARK,		BBIF1_TSYNC_MARK,	BBIF1_TSCK_MARK,
	BBIF1_TXD_MARK,		BBIF1_RSCK_MARK,	BBIF1_RSYNC_MARK,
	BBIF1_FLOW_MARK,	BB_RX_FLOW_N_MARK,

	/* BBIF2 */
	BBIF2_TSCK1_MARK,	BBIF2_TSYNC1_MARK,
	BBIF2_TXD1_MARK,	BBIF2_RXD_MARK,

	/* FSI */
	FSIACK_MARK,	FSIBCK_MARK,		FSIAILR_MARK,	FSIAIBT_MARK,
	FSIAISLD_MARK,	FSIAOMC_MARK,		FSIAOLR_MARK,	FSIAOBT_MARK,
	FSIAOSLD_MARK,	FSIASPDIF_11_MARK,	FSIASPDIF_15_MARK,

	/* FMSI */
	FMSOCK_MARK,	FMSOOLR_MARK,	FMSIOLR_MARK,	FMSOOBT_MARK,
	FMSIOBT_MARK,	FMSOSLD_MARK,	FMSOILR_MARK,	FMSIILR_MARK,
	FMSOIBT_MARK,	FMSIIBT_MARK,	FMSISLD_MARK,	FMSICK_MARK,

	/* SCIFA0 */
	SCIFA0_TXD_MARK,	SCIFA0_RXD_MARK,	SCIFA0_SCK_MARK,
	SCIFA0_RTS_MARK,	SCIFA0_CTS_MARK,

	/* SCIFA1 */
	SCIFA1_TXD_MARK,	SCIFA1_RXD_MARK,	SCIFA1_SCK_MARK,
	SCIFA1_RTS_MARK,	SCIFA1_CTS_MARK,

	/* SCIFA2 */
	SCIFA2_CTS1_MARK,	SCIFA2_RTS1_MARK,	SCIFA2_TXD1_MARK,
	SCIFA2_RXD1_MARK,	SCIFA2_SCK1_MARK,

	/* SCIFA3 */
	SCIFA3_CTS_43_MARK,	SCIFA3_CTS_140_MARK,	SCIFA3_RTS_44_MARK,
	SCIFA3_RTS_141_MARK,	SCIFA3_SCK_MARK,	SCIFA3_TXD_MARK,
	SCIFA3_RXD_MARK,

	/* SCIFA4 */
	SCIFA4_RXD_MARK,	SCIFA4_TXD_MARK,

	/* SCIFA5 */
	SCIFA5_RXD_MARK,	SCIFA5_TXD_MARK,

	/* SCIFB */
	SCIFB_SCK_MARK,	SCIFB_RTS_MARK,	SCIFB_CTS_MARK,
	SCIFB_TXD_MARK,	SCIFB_RXD_MARK,

	/* CEU */
	VIO_HD_MARK,	VIO_CKO1_MARK,	VIO_CKO2_MARK,	VIO_VD_MARK,
	VIO_CLK_MARK,	VIO_FIELD_MARK,	VIO_CKO_MARK,
	VIO_D0_MARK,	VIO_D1_MARK,	VIO_D2_MARK,	VIO_D3_MARK,
	VIO_D4_MARK,	VIO_D5_MARK,	VIO_D6_MARK,	VIO_D7_MARK,
	VIO_D8_MARK,	VIO_D9_MARK,	VIO_D10_MARK,	VIO_D11_MARK,
	VIO_D12_MARK,	VIO_D13_MARK,	VIO_D14_MARK,	VIO_D15_MARK,

	/* USB0 */
	IDIN_0_MARK,	EXTLP_0_MARK,	OVCN2_0_MARK,	PWEN_0_MARK,
	OVCN_0_MARK,	VBUS0_0_MARK,

	/* USB1 */
	IDIN_1_18_MARK,		IDIN_1_113_MARK,
	PWEN_1_115_MARK,	PWEN_1_138_MARK,
	OVCN_1_114_MARK,	OVCN_1_162_MARK,
	EXTLP_1_MARK,		OVCN2_1_MARK,
	VBUS0_1_MARK,

	/* GPIO */