aiot/efElectricAgingTrendMining/dataSharedMemory/memoryOperation.h

/*
 * OMAP44xx Power Management register bits
 *
 * Copyright (C) 2009-2010 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H


/*
 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 * PRM_LDO_SRAM_MPU_SETUP
 */
#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT				1
#define OMAP4430_ABBOFF_ACT_EXPORT_MASK					(1 << 1)

/*
 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 * PRM_LDO_SRAM_MPU_SETUP
 */
#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT				2
#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK				(1 << 2)

/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_ABB_IVA_DONE_EN_SHIFT					31
#define OMAP4430_ABB_IVA_DONE_EN_MASK					(1 << 31)

/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_ABB_IVA_DONE_ST_SHIFT					31
#define OMAP4430_ABB_IVA_DONE_ST_MASK					(1 << 31)

/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_ABB_MPU_DONE_EN_SHIFT					7
#define OMAP4430_ABB_MPU_DONE_EN_MASK					(1 << 7)

/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_ABB_MPU_DONE_ST_SHIFT					7
#define OMAP4430_ABB_MPU_DONE_ST_MASK					(1 << 7)

/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_ACTIVE_FBB_SEL_SHIFT					2
#define OMAP4430_ACTIVE_FBB_SEL_MASK					(1 << 2)

/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_ACTIVE_RBB_SEL_SHIFT					1
#define OMAP4430_ACTIVE_RBB_SEL_MASK					(1 << 1)

/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_AESSMEM_ONSTATE_SHIFT					16
#define OMAP4430_AESSMEM_ONSTATE_MASK					(0x3 << 16)

/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_AESSMEM_RETSTATE_SHIFT					8
#define OMAP4430_AESSMEM_RETSTATE_MASK					(1 << 8)

/* Used by PM_ABE_PWRSTST */
#define OMAP4430_AESSMEM_STATEST_SHIFT					4
#define OMAP4430_AESSMEM_STATEST_MASK					(0x3 << 4)

/*
 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 * PRM_LDO_SRAM_MPU_SETUP
 */
#define OMAP4430_AIPOFF_SHIFT						8
#define OMAP4430_AIPOFF_MASK						(1 << 8)

/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT				0
#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK				(0x3 << 0)

/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT				4
#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK				(0x3 << 4)

/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT				2
#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK				(0x3 << 2)

/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_RA_ERR_SHIFT					25
#define OMAP4430_BYPS_RA_ERR_MASK					(1 << 25)

/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_SA_ERR_SHIFT					24
#define OMAP4430_BYPS_SA_ERR_MASK					(1 << 24)

/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT					26
#define OMAP4430_BYPS_TIMEOUT_ERR_MASK					(1 << 26)

/* Used by PRM_RSTST */
#define OMAP4430_C2C_RST_SHIFT						10
#define OMAP4430_C2C_RST_MASK						(1 << 10)

/* Used by PM_CAM_PWRSTCTRL */
#define OMAP4430_CAM_MEM_ONSTATE_SHIFT					16
#define OMAP4430_CAM_MEM_ONSTATE_MASK					(0x3 << 16)

/* Used by PM_CAM_PWRSTST */
#define OMAP4430_CAM_MEM_STATEST_SHIFT					4
#define OMAP4430_CAM_MEM_STATEST_MASK					(0x3 << 4)

/* Used by PRM_CLKREQCTRL */
#define OMAP4430_CLKREQ_COND_SHIFT					0
#define OMAP4430_CLKREQ_COND_MASK					(0x7 << 0)

/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT					0
#define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)

/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT					8
#define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)

/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT					16
#define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)

/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_CMD_VDD_CORE_L_SHIFT					4
#define OMAP4430_CMD_VDD_CORE_L_MASK					(1 << 4)